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decoder.c

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00001 /* 00002 * $Id: decoder.c,v 1.34 2003/12/02 08:24:59 troth Exp $ 00003 * 00004 **************************************************************************** 00005 * 00006 * simulavr - A simulator for the Atmel AVR family of microcontrollers. 00007 * Copyright (C) 2001, 2002, 2003 Theodore A. Roth 00008 * 00009 * This program is free software; you can redistribute it and/or modify 00010 * it under the terms of the GNU General Public License as published by 00011 * the Free Software Foundation; either version 2 of the License, or 00012 * (at your option) any later version. 00013 * 00014 * This program is distributed in the hope that it will be useful, 00015 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00017 * GNU General Public License for more details. 00018 * 00019 * You should have received a copy of the GNU General Public License 00020 * along with this program; if not, write to the Free Software 00021 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00022 * 00023 **************************************************************************** 00024 */ 00025 00026 /** 00027 * \file decoder.c 00028 * \brief Module for handling opcode decoding. 00029 * 00030 * The heart of the instruction decoder is the decode_opcode() function. 00031 * 00032 * The decode_opcode() function examines the given opcode to 00033 * determine which instruction applies and returns a pointer to a function to 00034 * handler performing the instruction's operation. If the given opcode does 00035 * not map to an instruction handler, NULL is returned. 00036 * 00037 * Nearly every instruction in Atmel's Instruction Set Data Sheet will have a 00038 * handler function defined. Each handler will perform all the operations 00039 * described in the data sheet for a given instruction. A few instructions 00040 * have synonyms. For example, CBR is a synonym for ANDI. 00041 * 00042 * This should all be fairly straight forward. 00043 */ 00044 00045 #include <config.h> 00046 00047 #include <stdio.h> 00048 #include <stdlib.h> 00049 00050 #include "avrerror.h" 00051 #include "avrmalloc.h" 00052 #include "avrclass.h" 00053 #include "utils.h" 00054 #include "callback.h" 00055 #include "op_names.h" 00056 00057 #include "storage.h" 00058 #include "flash.h" 00059 00060 #include "vdevs.h" 00061 #include "memory.h" 00062 #include "stack.h" 00063 #include "register.h" 00064 #include "sram.h" 00065 #include "eeprom.h" 00066 #include "timers.h" 00067 #include "ports.h" 00068 00069 #include "avrcore.h" 00070 00071 #include "decoder.h" 00072 00073 struct opcode_info *global_opcode_lookup_table; 00074 00075 /** \brief Masks to help extracting information from opcodes. */ 00076 00077 enum decoder_operand_masks 00078 { 00079 /** 2 bit register id ( R24, R26, R28, R30 ) */ 00080 mask_Rd_2 = 0x0030, 00081 /** 3 bit register id ( R16 - R23 ) */ 00082 mask_Rd_3 = 0x0070, 00083 /** 4 bit register id ( R16 - R31 ) */ 00084 mask_Rd_4 = 0x00f0, 00085 /** 5 bit register id ( R00 - R31 ) */ 00086 mask_Rd_5 = 0x01f0, 00087 00088 /** 3 bit register id ( R16 - R23 ) */ 00089 mask_Rr_3 = 0x0007, 00090 /** 4 bit register id ( R16 - R31 ) */ 00091 mask_Rr_4 = 0x000f, 00092 /** 5 bit register id ( R00 - R31 ) */ 00093 mask_Rr_5 = 0x020f, 00094 00095 /** for 8 bit constant */ 00096 mask_K_8 = 0x0F0F, 00097 /** for 6 bit constant */ 00098 mask_K_6 = 0x00CF, 00099 00100 /** for 7 bit relative address */ 00101 mask_k_7 = 0x03F8, 00102 /** for 12 bit relative address */ 00103 mask_k_12 = 0x0FFF, 00104 /** for 22 bit absolute address */ 00105 mask_k_22 = 0x01F1, 00106 00107 /** register bit select */ 00108 mask_reg_bit = 0x0007, 00109 /** status register bit select */ 00110 mask_sreg_bit = 0x0070, 00111 /** address displacement (q) */ 00112 mask_q_displ = 0x2C07, 00113 00114 /** 5 bit register id ( R00 - R31 ) */ 00115 mask_A_5 = 0x00F8, 00116 /** 6 bit IO port id */ 00117 mask_A_6 = 0x060F, 00118 }; 00119 00120 /* Some handlers need predeclared */ 00121 static int avr_op_CALL (AvrCore *core, uint16_t opcode, unsigned int arg1, 00122 unsigned int arg2); 00123 static int avr_op_JMP (AvrCore *core, uint16_t opcode, unsigned int arg1, 00124 unsigned int arg2); 00125 static int avr_op_LDS (AvrCore *core, uint16_t opcode, unsigned int arg1, 00126 unsigned int arg2); 00127 static int avr_op_STS (AvrCore *core, uint16_t opcode, unsigned int arg1, 00128 unsigned int arg2); 00129 00130 /****************************************************************************\ 00131 * 00132 * Helper functions to extract information from the opcodes. 00133 * 00134 \***************************************************************************/ 00135 00136 static inline int 00137 get_rd_2 (uint16_t opcode) 00138 { 00139 int reg = ((opcode & mask_Rd_2) >> 4) & 0x3; 00140 return (reg * 2) + 24; 00141 } 00142 00143 static inline int 00144 get_rd_3 (uint16_t opcode) 00145 { 00146 int reg = opcode & mask_Rd_3; 00147 return ((reg >> 4) & 0x7) + 16; 00148 } 00149 00150 static inline int 00151 get_rd_4 (uint16_t opcode) 00152 { 00153 int reg = opcode & mask_Rd_4; 00154 return ((reg >> 4) & 0xf) + 16; 00155 } 00156 00157 static inline int 00158 get_rd_5 (uint16_t opcode) 00159 { 00160 int reg = opcode & mask_Rd_5; 00161 return ((reg >> 4) & 0x1f); 00162 } 00163 00164 static inline int 00165 get_rr_3 (uint16_t opcode) 00166 { 00167 return (opcode & mask_Rr_3) + 16; 00168 } 00169 00170 static inline int 00171 get_rr_4 (uint16_t opcode) 00172 { 00173 return (opcode & mask_Rr_4) + 16; 00174 } 00175 00176 static inline int 00177 get_rr_5 (uint16_t opcode) 00178 { 00179 int reg = opcode & mask_Rr_5; 00180 return (reg & 0xf) + ((reg >> 5) & 0x10); 00181 } 00182 00183 static inline uint8_t 00184 get_K_8 (uint16_t opcode) 00185 { 00186 int K = opcode & mask_K_8; 00187 return ((K >> 4) & 0xf0) + (K & 0xf); 00188 } 00189 00190 static inline uint8_t 00191 get_K_6 (uint16_t opcode) 00192 { 00193 int K = opcode & mask_K_6; 00194 return ((K >> 2) & 0x0030) + (K & 0xf); 00195 } 00196 00197 static inline int 00198 get_k_7 (uint16_t opcode) 00199 { 00200 return (((opcode & mask_k_7) >> 3) & 0x7f); 00201 } 00202 00203 static inline int 00204 get_k_12 (uint16_t opcode) 00205 { 00206 return (opcode & mask_k_12); 00207 } 00208 00209 static inline int 00210 get_k_22 (uint16_t opcode) 00211 { 00212 /* Masks only the upper 6 bits of the address, the other 16 bits 00213 * are in PC + 1. */ 00214 int k = opcode & mask_k_22; 00215 return ((k >> 3) & 0x003e) + (k & 0x1); 00216 } 00217 00218 static inline int 00219 get_reg_bit (uint16_t opcode) 00220 { 00221 return opcode & mask_reg_bit; 00222 } 00223 00224 static inline int 00225 get_sreg_bit (uint16_t opcode) 00226 { 00227 return (opcode & mask_sreg_bit) >> 4; 00228 } 00229 00230 static inline int 00231 get_q (uint16_t opcode) 00232 { 00233 /* 00q0 qq00 0000 0qqq : Yuck! */ 00234 int q = opcode & mask_q_displ; 00235 int qq = (((q >> 1) & 0x1000) + (q & 0x0c00)) >> 7; 00236 return (qq & 0x0038) + (q & 0x7); 00237 } 00238 00239 static inline int 00240 get_A_5 (uint16_t opcode) 00241 { 00242 return (opcode & mask_A_5) >> 3; 00243 } 00244 00245 static inline int 00246 get_A_6 (uint16_t opcode) 00247 { 00248 int A = opcode & mask_A_6; 00249 return ((A >> 5) & 0x0030) + (A & 0xf); 00250 } 00251 00252 /****************************************************************************\ 00253 * 00254 * Helper functions for calculating the status register bit values. 00255 * See the Atmel data sheet for the instuction set for more info. 00256 * 00257 \****************************************************************************/ 00258 00259 static inline int 00260 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b) 00261 { 00262 uint8_t resb = res >> b & 0x1; 00263 uint8_t rdb = rd >> b & 0x1; 00264 uint8_t rrb = rr >> b & 0x1; 00265 return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb); 00266 } 00267 00268 static inline int 00269 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr) 00270 { 00271 uint8_t res7 = res >> 7 & 0x1; 00272 uint8_t rd7 = rd >> 7 & 0x1; 00273 uint8_t rr7 = rr >> 7 & 0x1; 00274 return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7); 00275 } 00276 00277 static inline int 00278 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b) 00279 { 00280 uint8_t resb = res >> b & 0x1; 00281 uint8_t rdb = rd >> b & 0x1; 00282 uint8_t rrb = rr >> b & 0x1; 00283 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb); 00284 } 00285 00286 static inline int 00287 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr) 00288 { 00289 uint8_t res7 = res >> 7 & 0x1; 00290 uint8_t rd7 = rd >> 7 & 0x1; 00291 uint8_t rr7 = rr >> 7 & 0x1; 00292 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7); 00293 } 00294 00295 static inline int 00296 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b) 00297 { 00298 uint8_t resb = res >> b & 0x1; 00299 uint8_t rdb = rd >> b & 0x1; 00300 uint8_t rrb = rr >> b & 0x1; 00301 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb); 00302 } 00303 00304 static inline int 00305 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr) 00306 { 00307 uint8_t res7 = res >> 7 & 0x1; 00308 uint8_t rd7 = rd >> 7 & 0x1; 00309 uint8_t rr7 = rr >> 7 & 0x1; 00310 /* The atmel data sheet says the second term is ~rd7 for CP 00311 * but that doesn't make any sense. You be the judge. */ 00312 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7); 00313 } 00314 00315 /****************************************************************************\ 00316 * 00317 * Misc Helper functions 00318 * 00319 \****************************************************************************/ 00320 00321 static inline int 00322 is_next_inst_2_words (AvrCore *core) 00323 { 00324 /* See if next is a two word instruction 00325 * CALL, JMP, LDS, and STS are the only two word (32 bit) instructions. */ 00326 uint16_t next_opcode = 00327 flash_read (core->flash, avr_core_PC_get (core) + 1); 00328 struct opcode_info *opi = decode_opcode (next_opcode); 00329 00330 return ((opi->func == avr_op_CALL) || (opi->func == avr_op_JMP) 00331 || (opi->func == avr_op_LDS) || (opi->func == avr_op_STS)); 00332 } 00333 00334 static inline int 00335 n_bit_unsigned_to_signed (unsigned int val, int n) 00336 { 00337 /* Convert n-bit unsigned value to a signed value. */ 00338 unsigned int mask; 00339 00340 if ((val & (1 << (n - 1))) == 0) 00341 return (int)val; 00342 00343 /* manually calculate two's complement */ 00344 mask = (1 << n) - 1; 00345 return -1 * ((~val & mask) + 1); 00346 } 00347 00348 /****************************************************************************\ 00349 * 00350 * Opcode handler functions. 00351 * 00352 \****************************************************************************/ 00353 00354 static int 00355 avr_op_ADC (AvrCore *core, uint16_t opcode, unsigned int arg1, 00356 unsigned int arg2) 00357 { 00358 /* 00359 * Add with Carry. 00360 * 00361 * Opcode : 0001 11rd dddd rrrr 00362 * Usage : ADC Rd, Rr 00363 * Operation : Rd <- Rd + Rr + C 00364 * Flags : Z,C,N,V,S,H 00365 * Num Clocks : 1 00366 */ 00367 int H, V, N, S, Z, C; 00368 00369 int Rd = arg1; 00370 int Rr = arg2; 00371 00372 uint8_t rd = avr_core_gpwr_get (core, Rd); 00373 uint8_t rr = avr_core_gpwr_get (core, Rr); 00374 00375 uint8_t res = rd + rr + avr_core_sreg_get_bit (core, SREG_C); 00376 00377 uint8_t sreg = avr_core_sreg_get (core); 00378 00379 sreg = set_bit_in_byte (sreg, SREG_H, H = get_add_carry (res, rd, rr, 3)); 00380 sreg = set_bit_in_byte (sreg, SREG_V, V = get_add_overflow (res, rd, rr)); 00381 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00382 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00383 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 00384 sreg = set_bit_in_byte (sreg, SREG_C, C = get_add_carry (res, rd, rr, 7)); 00385 00386 avr_core_sreg_set (core, sreg); 00387 00388 avr_core_gpwr_set (core, Rd, res); 00389 avr_core_PC_incr (core, 1); 00390 avr_core_inst_CKS_set (core, 1); 00391 00392 return opcode_ADC; 00393 } 00394 00395 static int 00396 avr_op_ADD (AvrCore *core, uint16_t opcode, unsigned int arg1, 00397 unsigned int arg2) 00398 { 00399 /* 00400 * Add without Carry. 00401 * 00402 * Opcode : 0000 11rd dddd rrrr 00403 * Usage : ADD Rd, Rr 00404 * Operation : Rd <- Rd + Rr 00405 * Flags : Z,C,N,V,S,H 00406 * Num Clocks : 1 00407 */ 00408 int H, V, N, S, Z, C; 00409 00410 int Rd = arg1; 00411 int Rr = arg2; 00412 00413 uint8_t rd = avr_core_gpwr_get (core, Rd); 00414 uint8_t rr = avr_core_gpwr_get (core, Rr); 00415 00416 uint8_t res = rd + rr; 00417 00418 uint8_t sreg = avr_core_sreg_get (core); 00419 00420 sreg = set_bit_in_byte (sreg, SREG_H, H = get_add_carry (res, rd, rr, 3)); 00421 sreg = set_bit_in_byte (sreg, SREG_V, V = get_add_overflow (res, rd, rr)); 00422 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00423 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00424 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 00425 sreg = set_bit_in_byte (sreg, SREG_C, C = get_add_carry (res, rd, rr, 7)); 00426 00427 avr_core_sreg_set (core, sreg); 00428 00429 avr_core_gpwr_set (core, Rd, res); 00430 avr_core_PC_incr (core, 1); 00431 avr_core_inst_CKS_set (core, 1); 00432 00433 return opcode_ADD; 00434 } 00435 00436 static int 00437 avr_op_ADIW (AvrCore *core, uint16_t opcode, unsigned int arg1, 00438 unsigned int arg2) 00439 { 00440 /* 00441 * Add Immediate to Word. 00442 * 00443 * Opcode : 1001 0110 KKdd KKKK 00444 * Usage : ADIW Rd, K 00445 * Operation : Rd+1:Rd <- Rd+1:Rd + K 00446 * Flags : Z,C,N,V,S 00447 * Num Clocks : 2 00448 */ 00449 int C, Z, S, N, V; 00450 00451 int Rd = arg1; 00452 uint8_t K = arg2; 00453 00454 uint8_t rdl = avr_core_gpwr_get (core, Rd); 00455 uint8_t rdh = avr_core_gpwr_get (core, Rd + 1); 00456 00457 uint16_t rd = (rdh << 8) + rdl; 00458 uint16_t res = rd + K; 00459 00460 uint8_t sreg = avr_core_sreg_get (core); 00461 00462 sreg = set_bit_in_byte (sreg, SREG_V, V = 00463 (~(rdh >> 7 & 0x1) & (res >> 15 & 0x1))); 00464 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 15) & 0x1)); 00465 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00466 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xffff) == 0)); 00467 sreg = set_bit_in_byte (sreg, SREG_C, C = 00468 (~(res >> 15 & 0x1) & (rdh >> 7 & 0x1))); 00469 00470 avr_core_sreg_set (core, sreg); 00471 00472 avr_core_gpwr_set (core, Rd, res & 0xff); 00473 avr_core_gpwr_set (core, Rd + 1, res >> 8); 00474 00475 avr_core_PC_incr (core, 1); 00476 avr_core_inst_CKS_set (core, 2); 00477 00478 return opcode_ADIW; 00479 } 00480 00481 static int 00482 avr_op_AND (AvrCore *core, uint16_t opcode, unsigned int arg1, 00483 unsigned int arg2) 00484 { 00485 /* 00486 * Logical AND. 00487 * 00488 * Opcode : 0010 00rd dddd rrrr 00489 * Usage : AND Rd, Rr 00490 * Operation : Rd <- Rd & Rr 00491 * Flags : Z,N,V,S 00492 * Num Clocks : 1 00493 */ 00494 int Z, N, V, S; 00495 00496 int Rd = arg1; 00497 int Rr = arg2; 00498 00499 uint8_t rd = avr_core_gpwr_get (core, Rd); 00500 uint8_t rr = avr_core_gpwr_get (core, Rr); 00501 uint8_t res = rd & rr; 00502 00503 uint8_t sreg = avr_core_sreg_get (core); 00504 00505 sreg = set_bit_in_byte (sreg, SREG_V, V = 0); 00506 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00507 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00508 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 00509 00510 avr_core_sreg_set (core, sreg); 00511 00512 avr_core_gpwr_set (core, Rd, res); 00513 avr_core_PC_incr (core, 1); 00514 avr_core_inst_CKS_set (core, 1); 00515 00516 return opcode_AND; 00517 } 00518 00519 static int 00520 avr_op_ANDI (AvrCore *core, uint16_t opcode, unsigned int arg1, 00521 unsigned int arg2) 00522 { 00523 /* 00524 * Logical AND with Immed. 00525 * 00526 * Opcode : 0111 KKKK dddd KKKK 00527 * Usage : ANDI Rd, K 00528 * Operation : Rd <- Rd & K 00529 * Flags : Z,N,V,S 00530 * Num Clocks : 1 00531 */ 00532 int Z, N, V, S; 00533 00534 int Rd = arg1; 00535 uint8_t K = arg2; 00536 00537 uint8_t rd = avr_core_gpwr_get (core, Rd); 00538 uint8_t res = rd & K; 00539 00540 uint8_t sreg = avr_core_sreg_get (core); 00541 00542 sreg = set_bit_in_byte (sreg, SREG_V, V = 0); 00543 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00544 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00545 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 00546 00547 avr_core_sreg_set (core, sreg); 00548 00549 avr_core_gpwr_set (core, Rd, res); 00550 avr_core_PC_incr (core, 1); 00551 avr_core_inst_CKS_set (core, 1); 00552 00553 return opcode_ANDI; 00554 } 00555 00556 static int 00557 avr_op_ASR (AvrCore *core, uint16_t opcode, unsigned int arg1, 00558 unsigned int arg2) 00559 { 00560 /* 00561 * Arithmetic Shift Right. 00562 * 00563 * Opcode : 1001 010d dddd 0101 00564 * Usage : ASR Rd 00565 * Operation : Rd(n) <- Rd(n+1), n=0..6 00566 * Flags : Z,C,N,V,S 00567 * Num Clocks : 1 00568 */ 00569 int Z, C, N, V, S; 00570 00571 int Rd = arg1; 00572 00573 uint8_t rd = avr_core_gpwr_get (core, Rd); 00574 uint8_t res = (rd >> 1) + (rd & 0x80); 00575 00576 uint8_t sreg = avr_core_sreg_get (core); 00577 00578 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00579 sreg = set_bit_in_byte (sreg, SREG_C, C = (rd & 0x1)); 00580 sreg = set_bit_in_byte (sreg, SREG_V, V = (N ^ C)); 00581 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00582 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 00583 00584 avr_core_sreg_set (core, sreg); 00585 00586 avr_core_gpwr_set (core, Rd, res); 00587 avr_core_PC_incr (core, 1); 00588 avr_core_inst_CKS_set (core, 1); 00589 00590 return opcode_ASR; 00591 } 00592 00593 static int 00594 avr_op_BCLR (AvrCore *core, uint16_t opcode, unsigned int arg1, 00595 unsigned int arg2) 00596 { 00597 /* 00598 * Clear a single flag or bit in SREG. 00599 * 00600 * Opcode : 1001 0100 1sss 1000 00601 * Usage : BCLR 00602 * Operation : SREG(s) <- 0 00603 * Flags : SREG(s) 00604 * Num Clocks : 1 00605 */ 00606 avr_core_sreg_set_bit (core, arg1, 0); 00607 avr_core_PC_incr (core, 1); 00608 avr_core_inst_CKS_set (core, 1); 00609 00610 return opcode_BCLR; 00611 } 00612 00613 static int 00614 avr_op_BLD (AvrCore *core, uint16_t opcode, unsigned int arg1, 00615 unsigned int arg2) 00616 { 00617 /* Bit load from T to Register. 00618 * 00619 * Opcode : 1111 100d dddd 0bbb 00620 * Usage : BLD Rd, b 00621 * Operation : Rd(b) <- T 00622 * Flags : None 00623 * Num Clocks : 1 00624 */ 00625 int Rd = arg1; 00626 int bit = arg2; 00627 00628 uint8_t rd = avr_core_gpwr_get (core, Rd); 00629 int T = avr_core_sreg_get_bit (core, SREG_T); 00630 uint8_t res; 00631 00632 if (T == 0) 00633 res = rd & ~(1 << bit); 00634 else 00635 res = rd | (1 << bit); 00636 00637 avr_core_gpwr_set (core, Rd, res); 00638 avr_core_PC_incr (core, 1); 00639 avr_core_inst_CKS_set (core, 1); 00640 00641 return opcode_BLD; 00642 } 00643 00644 static int 00645 avr_op_BRBC (AvrCore *core, uint16_t opcode, unsigned int arg1, 00646 unsigned int arg2) 00647 { 00648 /* 00649 * Branch if Status Flag Cleared. 00650 * 00651 * Pass control directly to the specific bit operation. 00652 * 00653 * Opcode : 1111 01kk kkkk ksss 00654 * Usage : BRBC s, k 00655 * Operation : if (SREG(s) = 0) then PC <- PC + k + 1 00656 * Flags : None 00657 * Num Clocks : 1 / 2 00658 * 00659 * k is an relative address represented in two's complements. 00660 * (64 < k <= 64) 00661 */ 00662 int bit = arg1; 00663 int k = arg2; 00664 00665 if (avr_core_sreg_get_bit (core, bit) == 0) 00666 { 00667 avr_core_PC_incr (core, k + 1); 00668 avr_core_inst_CKS_set (core, 2); 00669 } 00670 else 00671 { 00672 avr_core_PC_incr (core, 1); 00673 avr_core_inst_CKS_set (core, 1); 00674 } 00675 00676 return opcode_BRBC; 00677 } 00678 00679 static int 00680 avr_op_BRBS (AvrCore *core, uint16_t opcode, unsigned int arg1, 00681 unsigned int arg2) 00682 { 00683 /* 00684 * Branch if Status Flag Set. 00685 * 00686 * Pass control directly to the specific bit operation. 00687 * 00688 * Opcode : 1111 00kk kkkk ksss 00689 * Usage : BRBS s, k 00690 * Operation : if (SREG(s) = 1) then PC <- PC + k + 1 00691 * Flags : None 00692 * Num Clocks : 1 / 2 00693 * 00694 * k is an relative address represented in two's complements. 00695 * (64 < k <= 64) 00696 */ 00697 int bit = arg1; 00698 int k = arg2; 00699 00700 if (avr_core_sreg_get_bit (core, bit) != 0) 00701 { 00702 avr_core_PC_incr (core, k + 1); 00703 avr_core_inst_CKS_set (core, 2); 00704 } 00705 else 00706 { 00707 avr_core_PC_incr (core, 1); 00708 avr_core_inst_CKS_set (core, 1); 00709 } 00710 00711 return opcode_BRBS; 00712 } 00713 00714 static int 00715 avr_op_BREAK (AvrCore *core, uint16_t opcode, unsigned int arg1, 00716 unsigned int arg2) 00717 { 00718 /* 00719 * The BREAK instruction only available on devices with JTAG support. We 00720 * use it to implement break points for all devices though. When the 00721 * debugger sets a break point we will replace the insn at the requested 00722 * PC with the BREAK insn and save the PC and original insn on the break 00723 * point list. Thus, we only need to walk the break point list when we 00724 * reach a break insn. 00725 * 00726 * When a break occurs, we will return control to the caller _without_ 00727 * incrementing PC as the insn set datasheet says. 00728 * 00729 * Opcode : 1001 0101 1001 1000 00730 * Usage : BREAK 00731 * Operation : Puts the in Stopped Mode if supported, NOP otherwise. 00732 * Flags : None 00733 * Num Clocks : 1 00734 */ 00735 00736 /* FIXME: TRoth/2002-10-15: Should we execute the original insn which the 00737 break replaced here or let the caller handle that? For now we defer 00738 that to the caller. */ 00739 00740 /* return opcode_BREAK; */ 00741 return BREAK_POINT; 00742 } 00743 00744 static int 00745 avr_op_BSET (AvrCore *core, uint16_t opcode, unsigned int arg1, 00746 unsigned int arg2) 00747 { 00748 /* 00749 * Set a single flag or bit in SREG. 00750 * 00751 * Opcode : 1001 0100 0sss 1000 00752 * Usage : BSET 00753 * Operation : SREG(s) <- 1 00754 * Flags : SREG(s) 00755 * Num Clocks : 1 00756 */ 00757 avr_core_sreg_set_bit (core, arg1, 1); 00758 avr_core_PC_incr (core, 1); 00759 avr_core_inst_CKS_set (core, 1); 00760 00761 return opcode_BSET; 00762 } 00763 00764 static int 00765 avr_op_BST (AvrCore *core, uint16_t opcode, unsigned int arg1, 00766 unsigned int arg2) 00767 { 00768 /* 00769 * Bit Store from Register to T. 00770 * 00771 * Opcode : 1111 101d dddd 0bbb 00772 * Usage : BST Rd, b 00773 * Operation : T <- Rd(b) 00774 * Flags : T 00775 * Num Clocks : 1 00776 */ 00777 int Rd = arg1; 00778 int bit = arg2; 00779 00780 uint8_t rd = avr_core_gpwr_get (core, Rd); 00781 avr_core_sreg_set_bit (core, SREG_T, (rd >> bit) & 0x1); 00782 00783 avr_core_PC_incr (core, 1); 00784 avr_core_inst_CKS_set (core, 1); 00785 00786 return opcode_BST; 00787 } 00788 00789 static int 00790 avr_op_CALL (AvrCore *core, uint16_t opcode, unsigned int arg1, 00791 unsigned int arg2) 00792 { 00793 /* 00794 * Call Subroutine. 00795 * 00796 * Opcode : 1001 010k kkkk 111k kkkk kkkk kkkk kkkk 00797 * Usage : CALL k 00798 * Operation : PC <- k 00799 * Flags : None 00800 * Num Clocks : 4 / 5 00801 */ 00802 int pc = avr_core_PC_get (core); 00803 int pc_bytes = avr_core_PC_size (core); 00804 00805 int kh = arg1; 00806 int kl = flash_read (core->flash, pc + 1); 00807 00808 int k = (kh << 16) + kl; 00809 00810 if ((pc_bytes == 2) && (k > 0xffff)) 00811 avr_error ("Address out of allowed range: 0x%06x", k); 00812 00813 avr_core_stack_push (core, pc_bytes, pc + 2); 00814 00815 avr_core_PC_set (core, k); 00816 avr_core_inst_CKS_set (core, pc_bytes + 2); 00817 00818 return opcode_CALL; 00819 } 00820 00821 static int 00822 avr_op_CBI (AvrCore *core, uint16_t opcode, unsigned int arg1, 00823 unsigned int arg2) 00824 { 00825 /* 00826 * Clear Bit in I/O Register. 00827 * 00828 * Opcode : 1001 1000 AAAA Abbb 00829 * Usage : CBI A, b 00830 * Operation : I/O(A, b) <- 0 00831 * Flags : None 00832 * Num Clocks : 2 00833 */ 00834 int A = arg1; 00835 int b = arg2; 00836 00837 uint8_t val = avr_core_io_read (core, A); 00838 avr_core_io_write (core, A, val & ~(1 << b)); 00839 00840 avr_core_PC_incr (core, 1); 00841 avr_core_inst_CKS_set (core, 2); 00842 00843 return opcode_CBI; 00844 } 00845 00846 static int 00847 avr_op_COM (AvrCore *core, uint16_t opcode, unsigned int arg1, 00848 unsigned int arg2) 00849 { 00850 /* 00851 * One's Complement. 00852 * 00853 * Opcode : 1001 010d dddd 0000 00854 * Usage : COM Rd 00855 * Operation : Rd <- $FF - Rd 00856 * Flags : Z,C,N,V,S 00857 * Num Clocks : 1 00858 */ 00859 int Z, C, N, V, S; 00860 00861 int Rd = arg1; 00862 00863 uint8_t rd = avr_core_gpwr_get (core, Rd); 00864 uint8_t res = 0xff - rd; 00865 00866 uint8_t sreg = avr_core_sreg_get (core); 00867 00868 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00869 sreg = set_bit_in_byte (sreg, SREG_C, C = 1); 00870 sreg = set_bit_in_byte (sreg, SREG_V, V = 0); 00871 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00872 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 00873 00874 avr_core_sreg_set (core, sreg); 00875 00876 avr_core_gpwr_set (core, Rd, res); 00877 avr_core_PC_incr (core, 1); 00878 avr_core_inst_CKS_set (core, 1); 00879 00880 return opcode_COM; 00881 } 00882 00883 static int 00884 avr_op_CP (AvrCore *core, uint16_t opcode, unsigned int arg1, 00885 unsigned int arg2) 00886 { 00887 /* 00888 * Compare. 00889 * 00890 * Opcode : 0001 01rd dddd rrrr 00891 * Usage : CP Rd, Rr 00892 * Operation : Rd - Rr 00893 * Flags : Z,C,N,V,S,H 00894 * Num Clocks : 1 00895 */ 00896 int Z, C, N, V, S, H; 00897 00898 int Rd = arg1; 00899 int Rr = arg2; 00900 00901 uint8_t rd = avr_core_gpwr_get (core, Rd); 00902 uint8_t rr = avr_core_gpwr_get (core, Rr); 00903 uint8_t res = rd - rr; 00904 00905 uint8_t sreg = avr_core_sreg_get (core); 00906 00907 sreg = set_bit_in_byte (sreg, SREG_H, H = 00908 get_compare_carry (res, rd, rr, 3)); 00909 sreg = set_bit_in_byte (sreg, SREG_V, V = 00910 get_compare_overflow (res, rd, rr)); 00911 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00912 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00913 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 00914 sreg = set_bit_in_byte (sreg, SREG_C, C = 00915 get_compare_carry (res, rd, rr, 7)); 00916 00917 avr_core_sreg_set (core, sreg); 00918 00919 avr_core_PC_incr (core, 1); 00920 avr_core_inst_CKS_set (core, 1); 00921 00922 return opcode_CP; 00923 } 00924 00925 static int 00926 avr_op_CPC (AvrCore *core, uint16_t opcode, unsigned int arg1, 00927 unsigned int arg2) 00928 { 00929 /* 00930 * Compare with Carry. 00931 * 00932 * Opcode : 0000 01rd dddd rrrr 00933 * Usage : CPC Rd, Rr 00934 * Operation : Rd - Rr - C 00935 * Flags : Z,C,N,V,S,H 00936 * Num Clocks : 1 00937 */ 00938 int Z, C, N, V, S, H, prev_Z; 00939 00940 int Rd = arg1; 00941 int Rr = arg2; 00942 00943 uint8_t rd = avr_core_gpwr_get (core, Rd); 00944 uint8_t rr = avr_core_gpwr_get (core, Rr); 00945 uint8_t res = rd - rr - avr_core_sreg_get_bit (core, SREG_C); 00946 00947 uint8_t sreg = avr_core_sreg_get (core); 00948 00949 sreg = set_bit_in_byte (sreg, SREG_H, H = 00950 get_compare_carry (res, rd, rr, 3)); 00951 sreg = set_bit_in_byte (sreg, SREG_V, V = 00952 get_compare_overflow (res, rd, rr)); 00953 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00954 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 00955 sreg = set_bit_in_byte (sreg, SREG_C, C = 00956 get_compare_carry (res, rd, rr, 7)); 00957 00958 /* Previous value remains unchanged when result is 0; cleared otherwise */ 00959 Z = ((res & 0xff) == 0); 00960 prev_Z = avr_core_sreg_get_bit (core, SREG_Z); 00961 sreg = set_bit_in_byte (sreg, SREG_Z, Z && prev_Z); 00962 00963 avr_core_sreg_set (core, sreg); 00964 00965 avr_core_PC_incr (core, 1); 00966 avr_core_inst_CKS_set (core, 1); 00967 00968 return opcode_CPC; 00969 } 00970 00971 static int 00972 avr_op_CPI (AvrCore *core, uint16_t opcode, unsigned int arg1, 00973 unsigned int arg2) 00974 { 00975 /* 00976 * Compare with Immediate. 00977 * 00978 * Opcode : 0011 KKKK dddd KKKK 00979 * Usage : CPI Rd, K 00980 * Operation : Rd - K 00981 * Flags : Z,C,N,V,S,H 00982 * Num Clocks : 1 00983 */ 00984 int Z, C, N, V, S, H; 00985 00986 int Rd = arg1; 00987 uint8_t K = arg2; 00988 00989 uint8_t rd = avr_core_gpwr_get (core, Rd); 00990 uint8_t res = rd - K; 00991 00992 uint8_t sreg = avr_core_sreg_get (core); 00993 00994 sreg = set_bit_in_byte (sreg, SREG_H, H = 00995 get_compare_carry (res, rd, K, 3)); 00996 sreg = set_bit_in_byte (sreg, SREG_V, V = 00997 get_compare_overflow (res, rd, K)); 00998 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 00999 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 01000 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 01001 sreg = set_bit_in_byte (sreg, SREG_C, C = 01002 get_compare_carry (res, rd, K, 7)); 01003 01004 avr_core_sreg_set (core, sreg); 01005 01006 avr_core_PC_incr (core, 1); 01007 avr_core_inst_CKS_set (core, 1); 01008 01009 return opcode_CPI; 01010 } 01011 01012 static int 01013 avr_op_CPSE (AvrCore *core, uint16_t opcode, unsigned int arg1, 01014 unsigned int arg2) 01015 { 01016 /* 01017 * Compare, Skip if Equal. 01018 * 01019 * Opcode : 0001 00rd dddd rrrr 01020 * Usage : CPSE Rd, Rr 01021 * Operation : if (Rd = Rr) PC <- PC + 2 or 3 01022 * Flags : None 01023 * Num Clocks : 1 / 2 / 3 01024 */ 01025 int skip; 01026 01027 int Rd = arg1; 01028 int Rr = arg2; 01029 01030 uint8_t rd = avr_core_gpwr_get (core, Rd); 01031 uint8_t rr = avr_core_gpwr_get (core, Rr); 01032 01033 if (is_next_inst_2_words (core)) 01034 skip = 3; 01035 else 01036 skip = 2; 01037 01038 if (rd == rr) 01039 { 01040 avr_core_PC_incr (core, skip); 01041 avr_core_inst_CKS_set (core, skip); 01042 } 01043 else 01044 { 01045 avr_core_PC_incr (core, 1); 01046 avr_core_inst_CKS_set (core, 1); 01047 } 01048 01049 return opcode_CPSE; 01050 } 01051 01052 static int 01053 avr_op_DEC (AvrCore *core, uint16_t opcode, unsigned int arg1, 01054 unsigned int arg2) 01055 { 01056 /* 01057 * Decrement. 01058 * 01059 * Opcode : 1001 010d dddd 1010 01060 * Usage : DEC Rd 01061 * Operation : Rd <- Rd - 1 01062 * Flags : Z,N,V,S 01063 * Num Clocks : 1 01064 */ 01065 int Z, N, V, S; 01066 01067 int Rd = arg1; 01068 uint8_t rd = avr_core_gpwr_get (core, Rd); 01069 uint8_t res = rd - 1; 01070 01071 uint8_t sreg = avr_core_sreg_get (core); 01072 01073 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 01074 sreg = set_bit_in_byte (sreg, SREG_V, V = (rd == 0x80)); 01075 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 01076 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 01077 01078 avr_core_sreg_set (core, sreg); 01079 01080 avr_core_gpwr_set (core, Rd, res); 01081 01082 avr_core_PC_incr (core, 1); 01083 avr_core_inst_CKS_set (core, 1); 01084 01085 return opcode_DEC; 01086 } 01087 01088 static int 01089 avr_op_EICALL (AvrCore *core, uint16_t opcode, unsigned int arg1, 01090 unsigned int arg2) 01091 { 01092 /* 01093 * Extended Indirect Call to (Z). 01094 * 01095 * Opcode : 1001 0101 0001 1001 01096 * Usage : EICALL 01097 * Operation : PC(15:0) <- Z, PC(21:16) <- EIND 01098 * Flags : None 01099 * Num Clocks : 4 01100 */ 01101 int pc = avr_core_PC_get (core); 01102 int pc_bytes = 3; 01103 01104 /* Z is R31:R30 */ 01105 int new_pc = 01106 ((core->EIND & 0x3f) << 16) + (avr_core_gpwr_get (core, 31) << 8) + 01107 avr_core_gpwr_get (core, 30); 01108 01109 avr_warning ("needs serious code review\n"); 01110 01111 avr_core_stack_push (core, pc_bytes, pc + 1); 01112 01113 avr_core_PC_set (core, new_pc); 01114 avr_core_inst_CKS_set (core, 4); 01115 01116 return opcode_EICALL; 01117 } 01118 01119 static int 01120 avr_op_EIJMP (AvrCore *core, uint16_t opcode, unsigned int arg1, 01121 unsigned int arg2) 01122 { 01123 /* 01124 * Extended Indirect Jmp to (Z). 01125 * 01126 * Opcode : 1001 0100 0001 1001 01127 * Usage : EIJMP 01128 * Operation : PC(15:0) <- Z, PC(21:16) <- EIND 01129 * Flags : None 01130 * Num Clocks : 2 01131 */ 01132 01133 /* Z is R31:R30 */ 01134 int new_pc = 01135 ((core->EIND & 0x3f) << 16) + (avr_core_gpwr_get (core, 31) << 8) + 01136 avr_core_gpwr_get (core, 30); 01137 01138 avr_warning ("needs serious code review\n"); 01139 01140 avr_core_PC_set (core, new_pc); 01141 avr_core_inst_CKS_set (core, 2); 01142 01143 return opcode_EIJMP; 01144 } 01145 01146 static int 01147 avr_op_ELPM_Z (AvrCore *core, uint16_t opcode, unsigned int arg1, 01148 unsigned int arg2) 01149 { 01150 /* 01151 * Extended Load Program Memory. 01152 * 01153 * Opcode : 1001 000d dddd 0110 01154 * Usage : ELPM Rd, Z 01155 * Operation : R <- (RAMPZ:Z) 01156 * Flags : None 01157 * Num Clocks : 3 01158 */ 01159 int Z, high_byte, flash_addr; 01160 uint16_t data; 01161 01162 int Rd = arg1; 01163 01164 if ((Rd == 30) || (Rd == 31)) 01165 avr_error ("Results of operation are undefined"); 01166 01167 avr_warning ("needs serious code review\n"); 01168 01169 /* FIXME: Is this correct? */ 01170 /* Z is R31:R30 */ 01171 Z = ((avr_core_rampz_get (core) & 0x3f) << 16) + 01172 (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 01173 01174 high_byte = Z & 0x1; 01175 01176 flash_addr = Z / 2; 01177 01178 data = flash_read (core->flash, flash_addr); 01179 01180 if (high_byte == 1) 01181 avr_core_gpwr_set (core, Rd, data >> 8); 01182 else 01183 avr_core_gpwr_set (core, Rd, data & 0xff); 01184 01185 avr_core_PC_incr (core, 1); 01186 avr_core_inst_CKS_set (core, 3); 01187 01188 return opcode_ELPM_Z; 01189 } 01190 01191 static int 01192 avr_op_ELPM_Z_incr (AvrCore *core, uint16_t opcode, unsigned int arg1, 01193 unsigned int arg2) 01194 { 01195 /* 01196 * Extended Ld Prg Mem and Post-Incr. 01197 * 01198 * Opcode : 1001 000d dddd 0111 01199 * Usage : ELPM Rd, Z+ 01200 * Operation : Rd <- (RAMPZ:Z), Z <- Z + 1 01201 * Flags : None 01202 * Num Clocks : 3 01203 */ 01204 int Z, high_byte, flash_addr; 01205 uint16_t data; 01206 01207 int Rd = arg1; 01208 01209 if ((Rd == 30) || (Rd == 31)) 01210 avr_error ("Results of operation are undefined"); 01211 01212 /* TRoth/2002-08-14: This seems to work ok for me. */ 01213 /* avr_warning( "needs serious code review\n" ); */ 01214 01215 /* FIXME: Is this correct? */ 01216 /* Z is R31:R30 */ 01217 Z = ((avr_core_rampz_get (core) & 0x3f) << 16) + 01218 (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 01219 01220 high_byte = Z & 0x1; 01221 01222 flash_addr = Z / 2; 01223 01224 data = flash_read (core->flash, flash_addr); 01225 01226 if (high_byte == 1) 01227 avr_core_gpwr_set (core, Rd, data >> 8); 01228 else 01229 avr_core_gpwr_set (core, Rd, data & 0xff); 01230 01231 /* post increment Z */ 01232 Z += 1; 01233 avr_core_gpwr_set (core, 30, Z & 0xff); 01234 avr_core_gpwr_set (core, 31, Z >> 8); 01235 avr_core_rampz_set (core, (Z >> 16) & 0x3f); 01236 01237 avr_core_PC_incr (core, 1); 01238 avr_core_inst_CKS_set (core, 3); 01239 01240 return opcode_ELPM_Z_incr; 01241 } 01242 01243 static int 01244 avr_op_ELPM (AvrCore *core, uint16_t opcode, unsigned int arg1, 01245 unsigned int arg2) 01246 { 01247 /* 01248 * Extended Load Program Memory. 01249 * 01250 * This is the same as avr_op_ELPM_Z with Rd = R0. 01251 * 01252 * Opcode : 1001 0101 1101 1000 01253 * Usage : ELPM 01254 * Operation : R0 <- (RAMPZ:Z) 01255 * Flags : None 01256 * Num Clocks : 3 01257 */ 01258 avr_op_ELPM_Z (core, 0x9006, arg1, arg2); 01259 return opcode_ELPM; 01260 } 01261 01262 static int 01263 avr_op_EOR (AvrCore *core, uint16_t opcode, unsigned int arg1, 01264 unsigned int arg2) 01265 { 01266 /* 01267 * Exclusive OR. 01268 * 01269 * Opcode : 0010 01rd dddd rrrr 01270 * Usage : EOR Rd, Rr 01271 * Operation : Rd <- Rd ^ Rr 01272 * Flags : Z,N,V,S 01273 * Num Clocks : 1 01274 */ 01275 int Z, N, V, S; 01276 01277 int Rd = arg1; 01278 int Rr = arg2; 01279 01280 uint8_t rd = avr_core_gpwr_get (core, Rd); 01281 uint8_t rr = avr_core_gpwr_get (core, Rr); 01282 01283 uint8_t res = rd ^ rr; 01284 01285 uint8_t sreg = avr_core_sreg_get (core); 01286 01287 sreg = set_bit_in_byte (sreg, SREG_V, V = 0); 01288 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 01289 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 01290 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 01291 01292 avr_core_sreg_set (core, sreg); 01293 01294 avr_core_gpwr_set (core, Rd, res); 01295 01296 avr_core_PC_incr (core, 1); 01297 avr_core_inst_CKS_set (core, 1); 01298 01299 return opcode_EOR; 01300 } 01301 01302 static int 01303 avr_op_ESPM (AvrCore *core, uint16_t opcode, unsigned int arg1, 01304 unsigned int arg2) 01305 { 01306 /* 01307 * Extended Store Program Memory. 01308 * 01309 * Opcode : 1001 0101 1111 1000 01310 * Usage : ESPM 01311 * Operation : (RAMPZ:Z) <- R1:R0 01312 * Flags : None 01313 * Num Clocks : - 01314 */ 01315 avr_error ("This opcode is not implemented yet: 0x%04x", opcode); 01316 return opcode_ESPM; 01317 } 01318 01319 /** 01320 ** I don't know how this Fractional Multiplication works. 01321 ** If someone wishes to enlighten me, I write these. 01322 **/ 01323 01324 static int 01325 avr_op_FMUL (AvrCore *core, uint16_t opcode, unsigned int arg1, 01326 unsigned int arg2) 01327 { 01328 /* 01329 * Fractional Mult Unsigned. 01330 * 01331 * Opcode : 0000 0011 0ddd 1rrr 01332 * Usage : FMUL Rd, Rr 01333 * Operation : R1:R0 <- (Rd * Rr)<<1 (UU) 01334 * Flags : Z,C 01335 * Num Clocks : 2 01336 */ 01337 int Rd = arg1; 01338 int Rr = arg2; 01339 01340 uint8_t rd = avr_core_gpwr_get (core, Rd); 01341 uint8_t rr = avr_core_gpwr_get (core, Rr); 01342 01343 uint16_t resp = rd * rr; 01344 uint16_t res = resp << 1; 01345 01346 uint8_t sreg = avr_core_sreg_get (core); 01347 01348 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0)); 01349 sreg = set_bit_in_byte (sreg, SREG_C, ((resp >> 15) & 0x1)); 01350 01351 avr_core_sreg_set (core, sreg); 01352 01353 /* result goes in R1:R0 */ 01354 avr_core_gpwr_set (core, 1, res >> 8); 01355 avr_core_gpwr_set (core, 0, res & 0xff); 01356 01357 avr_core_PC_incr (core, 1); 01358 avr_core_inst_CKS_set (core, 2); 01359 01360 return opcode_FMUL; 01361 } 01362 01363 static int 01364 avr_op_FMULS (AvrCore *core, uint16_t opcode, unsigned int arg1, 01365 unsigned int arg2) 01366 { 01367 /* 01368 * Fractional Mult Signed. 01369 * 01370 * Opcode : 0000 0011 1ddd 0rrr 01371 * Usage : FMULS Rd, Rr 01372 * Operation : R1:R0 <- (Rd * Rr)<<1 (SS) 01373 * Flags : Z,C 01374 * Num Clocks : 2 01375 */ 01376 int Rd = arg1; 01377 int Rr = arg2; 01378 01379 int8_t rd = avr_core_gpwr_get (core, Rd); 01380 int8_t rr = avr_core_gpwr_get (core, Rr); 01381 01382 uint16_t resp = rd * rr; 01383 uint16_t res = resp << 1; 01384 01385 uint8_t sreg = avr_core_sreg_get (core); 01386 01387 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0)); 01388 sreg = set_bit_in_byte (sreg, SREG_C, ((resp >> 15) & 0x1)); 01389 01390 avr_core_sreg_set (core, sreg); 01391 01392 /* result goes in R1:R0 */ 01393 avr_core_gpwr_set (core, 1, res >> 8); 01394 avr_core_gpwr_set (core, 0, res & 0xff); 01395 01396 avr_core_PC_incr (core, 1); 01397 avr_core_inst_CKS_set (core, 2); 01398 01399 return opcode_FMULS; 01400 } 01401 01402 static int 01403 avr_op_FMULSU (AvrCore *core, uint16_t opcode, unsigned int arg1, 01404 unsigned int arg2) 01405 { 01406 /* 01407 * Fract Mult Signed w/ Unsigned. 01408 * 01409 * Opcode : 0000 0011 1ddd 1rrr 01410 * Usage : FMULSU Rd, Rr 01411 * Operation : R1:R0 <- (Rd * Rr)<<1 (SU) 01412 * Flags : Z,C 01413 * Num Clocks : 2 01414 */ 01415 int Rd = arg1; 01416 int Rr = arg2; 01417 01418 int8_t rd = avr_core_gpwr_get (core, Rd); 01419 uint8_t rr = avr_core_gpwr_get (core, Rr); 01420 01421 uint16_t resp = rd * rr; 01422 uint16_t res = resp << 1; 01423 01424 uint8_t sreg = avr_core_sreg_get (core); 01425 01426 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0)); 01427 sreg = set_bit_in_byte (sreg, SREG_C, ((resp >> 15) & 0x1)); 01428 01429 avr_core_sreg_set (core, sreg); 01430 01431 /* result goes in R1:R0 */ 01432 avr_core_gpwr_set (core, 1, res >> 8); 01433 avr_core_gpwr_set (core, 0, res & 0xff); 01434 01435 avr_core_PC_incr (core, 1); 01436 avr_core_inst_CKS_set (core, 2); 01437 01438 return opcode_FMULSU; 01439 } 01440 01441 static int 01442 avr_op_ICALL (AvrCore *core, uint16_t opcode, unsigned int arg1, 01443 unsigned int arg2) 01444 { 01445 /* 01446 * Indirect Call to (Z). 01447 * 01448 * Opcode : 1001 0101 0000 1001 01449 * Usage : ICALL 01450 * Operation : PC(15:0) <- Z, PC(21:16) <- 0 01451 * Flags : None 01452 * Num Clocks : 3 / 4 01453 */ 01454 int pc = avr_core_PC_get (core); 01455 int pc_bytes = avr_core_PC_size (core); 01456 01457 /* Z is R31:R30 */ 01458 int new_pc = 01459 (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 01460 01461 avr_core_stack_push (core, pc_bytes, pc + 1); 01462 01463 avr_core_PC_set (core, new_pc); 01464 avr_core_inst_CKS_set (core, pc_bytes + 1); 01465 01466 return opcode_ICALL; 01467 } 01468 01469 static int 01470 avr_op_IJMP (AvrCore *core, uint16_t opcode, unsigned int arg1, 01471 unsigned int arg2) 01472 { 01473 /* 01474 * Indirect Jump to (Z). 01475 * 01476 * Opcode : 1001 0100 0000 1001 01477 * Usage : IJMP 01478 * Operation : PC(15:0) <- Z, PC(21:16) <- 0 01479 * Flags : None 01480 * Num Clocks : 2 01481 */ 01482 01483 /* Z is R31:R30 */ 01484 int new_pc = 01485 (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 01486 avr_core_PC_set (core, new_pc); 01487 avr_core_inst_CKS_set (core, 2); 01488 01489 return opcode_IJMP; 01490 } 01491 01492 static int 01493 avr_op_IN (AvrCore *core, uint16_t opcode, unsigned int arg1, 01494 unsigned int arg2) 01495 { 01496 /* 01497 * In From I/O Location. 01498 * 01499 * Opcode : 1011 0AAd dddd AAAA 01500 * Usage : IN Rd, A 01501 * Operation : Rd <- I/O(A) 01502 * Flags : None 01503 * Num Clocks : 1 01504 */ 01505 int Rd = arg1; 01506 int A = arg2; 01507 01508 avr_core_gpwr_set (core, Rd, avr_core_io_read (core, A)); 01509 01510 avr_core_PC_incr (core, 1); 01511 avr_core_inst_CKS_set (core, 1); 01512 01513 return opcode_IN; 01514 } 01515 01516 static int 01517 avr_op_INC (AvrCore *core, uint16_t opcode, unsigned int arg1, 01518 unsigned int arg2) 01519 { 01520 /* 01521 * Increment. 01522 * 01523 * Opcode : 1001 010d dddd 0011 01524 * Usage : INC Rd 01525 * Operation : Rd <- Rd + 1 01526 * Flags : Z,N,V,S 01527 * Num Clocks : 1 01528 */ 01529 int Z, N, V, S; 01530 01531 int Rd = arg1; 01532 uint8_t rd = avr_core_gpwr_get (core, Rd); 01533 uint8_t res = rd + 1; 01534 01535 uint8_t sreg = avr_core_sreg_get (core); 01536 01537 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 01538 sreg = set_bit_in_byte (sreg, SREG_V, V = (rd == 0x7f)); 01539 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 01540 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 01541 01542 avr_core_sreg_set (core, sreg); 01543 01544 avr_core_gpwr_set (core, Rd, res); 01545 01546 avr_core_PC_incr (core, 1); 01547 avr_core_inst_CKS_set (core, 1); 01548 01549 return opcode_INC; 01550 } 01551 01552 static int 01553 avr_op_JMP (AvrCore *core, uint16_t opcode, unsigned int arg1, 01554 unsigned int arg2) 01555 { 01556 /* 01557 * Jump. 01558 * 01559 * Opcode : 1001 010k kkkk 110k kkkk kkkk kkkk kkkk 01560 * Usage : JMP k 01561 * Operation : PC <- k 01562 * Flags : None 01563 * Num Clocks : 3 01564 */ 01565 int kh = arg1; 01566 int kl = flash_read (core->flash, avr_core_PC_get (core) + 1); 01567 01568 int k = (kh << 16) + kl; 01569 01570 avr_core_PC_set (core, k); 01571 avr_core_inst_CKS_set (core, 3); 01572 01573 return opcode_JMP; 01574 } 01575 01576 static int 01577 avr_op_LDD_Y (AvrCore *core, uint16_t opcode, unsigned int arg1, 01578 unsigned int arg2) 01579 { 01580 /* 01581 * Load Indirect with Displacement using index Y. 01582 * 01583 * Opcode : 10q0 qq0d dddd 1qqq 01584 * Usage : LDD Rd, Y+q 01585 * Operation : Rd <- (Y + q) 01586 * Flags : None 01587 * Num Clocks : 2 01588 */ 01589 uint16_t Y; 01590 int Rd = arg1; 01591 int q = arg2; 01592 01593 /* Y is R29:R28 */ 01594 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28); 01595 01596 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Y + q)); 01597 01598 avr_core_PC_incr (core, 1); 01599 avr_core_inst_CKS_set (core, 2); 01600 01601 return opcode_LDD_Y; 01602 } 01603 01604 static int 01605 avr_op_LDD_Z (AvrCore *core, uint16_t opcode, unsigned int arg1, 01606 unsigned int arg2) 01607 { 01608 /* 01609 * Load Indirect with Displacement using index Z. 01610 * 01611 * Opcode : 10q0 qq0d dddd 0qqq 01612 * Usage : LDD Rd, Z+q 01613 * Operation : Rd <- (Z + q) 01614 * Flags : None 01615 * Num Clocks : 2 01616 */ 01617 uint16_t Z; 01618 01619 int Rd = arg1; 01620 int q = arg2; 01621 01622 /* Z is R31:R30 */ 01623 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 01624 01625 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Z + q)); 01626 01627 avr_core_PC_incr (core, 1); 01628 avr_core_inst_CKS_set (core, 2); 01629 01630 return opcode_LDD_Z; 01631 } 01632 01633 static int 01634 avr_op_LDI (AvrCore *core, uint16_t opcode, unsigned int arg1, 01635 unsigned int arg2) 01636 { 01637 /* 01638 * Load Immediate. 01639 * 01640 * Opcode : 1110 KKKK dddd KKKK 01641 * Usage : LDI Rd, K 01642 * Operation : Rd <- K 01643 * Flags : None 01644 * Num Clocks : 1 01645 */ 01646 int Rd = arg1; 01647 uint8_t K = arg2; 01648 01649 avr_core_gpwr_set (core, Rd, K); 01650 01651 avr_core_PC_incr (core, 1); 01652 avr_core_inst_CKS_set (core, 1); 01653 01654 return opcode_LDI; 01655 } 01656 01657 static int 01658 avr_op_LDS (AvrCore *core, uint16_t opcode, unsigned int arg1, 01659 unsigned int arg2) 01660 { 01661 /* 01662 * Load Direct from data space. 01663 * 01664 * Opcode : 1001 000d dddd 0000 kkkk kkkk kkkk kkkk 01665 * Usage : LDS Rd, k 01666 * Operation : Rd <- (k) 01667 * Flags : None 01668 * Num Clocks : 2 01669 */ 01670 int Rd = arg1; 01671 01672 /* Get data at k in current data segment and put into Rd */ 01673 int k_pc = avr_core_PC_get (core) + 1; 01674 int k = flash_read (core->flash, k_pc); 01675 01676 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, k)); 01677 01678 avr_core_PC_incr (core, 2); 01679 avr_core_inst_CKS_set (core, 2); 01680 01681 return opcode_LDS; 01682 } 01683 01684 static int 01685 avr_op_LD_X (AvrCore *core, uint16_t opcode, unsigned int arg1, 01686 unsigned int arg2) 01687 { 01688 /* 01689 * Load Indirect using index X. 01690 * 01691 * Opcode : 1001 000d dddd 1100 01692 * Usage : LD Rd, X 01693 * Operation : Rd <- (X) 01694 * Flags : None 01695 * Num Clocks : 2 01696 */ 01697 uint16_t X; 01698 01699 int Rd = arg1; 01700 01701 /* X is R27:R26 */ 01702 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26); 01703 01704 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, X)); 01705 01706 avr_core_PC_incr (core, 1); 01707 avr_core_inst_CKS_set (core, 2); 01708 01709 return opcode_LD_X; 01710 } 01711 01712 static int 01713 avr_op_LD_X_decr (AvrCore *core, uint16_t opcode, unsigned int arg1, 01714 unsigned int arg2) 01715 { 01716 /* 01717 * Load Indirect and Pre-Decrement using index X. 01718 * 01719 * Opcode : 1001 000d dddd 1110 01720 * Usage : LD Rd, -X 01721 * Operation : X <- X - 1, Rd <- (X) 01722 * Flags : None 01723 * Num Clocks : 2 01724 */ 01725 uint16_t X; 01726 01727 int Rd = arg1; 01728 01729 if ((Rd == 26) || (Rd == 27)) 01730 avr_error ("Results of operation are undefined"); 01731 01732 /* X is R27:R26 */ 01733 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26); 01734 01735 /* Perform pre-decrement */ 01736 X -= 1; 01737 avr_core_gpwr_set (core, 26, X & 0xff); 01738 avr_core_gpwr_set (core, 27, X >> 8); 01739 01740 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, X)); 01741 01742 avr_core_PC_incr (core, 1); 01743 avr_core_inst_CKS_set (core, 2); 01744 01745 return opcode_LD_X_decr; 01746 } 01747 01748 static int 01749 avr_op_LD_X_incr (AvrCore *core, uint16_t opcode, unsigned int arg1, 01750 unsigned int arg2) 01751 { 01752 /* 01753 * Load Indirect and Post-Increment using index X. 01754 * 01755 * Opcode : 1001 000d dddd 1101 01756 * Usage : LD Rd, X+ 01757 * Operation : Rd <- (X), X <- X + 1 01758 * Flags : None 01759 * Num Clocks : 2 01760 */ 01761 uint16_t X; 01762 01763 int Rd = arg1; 01764 01765 if ((Rd == 26) || (Rd == 27)) 01766 avr_error ("Results of operation are undefined"); 01767 01768 /* X is R27:R26 */ 01769 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26); 01770 01771 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, X)); 01772 01773 /* Perform post-increment */ 01774 X += 1; 01775 avr_core_gpwr_set (core, 26, X & 0xff); 01776 avr_core_gpwr_set (core, 27, X >> 8); 01777 01778 avr_core_PC_incr (core, 1); 01779 avr_core_inst_CKS_set (core, 2); 01780 01781 return opcode_LD_X_incr; 01782 } 01783 01784 static int 01785 avr_op_LD_Y_decr (AvrCore *core, uint16_t opcode, unsigned int arg1, 01786 unsigned int arg2) 01787 { 01788 /* 01789 * Load Indirect and PreDecrement using index Y. 01790 * 01791 * Opcode : 1001 000d dddd 1010 01792 * Usage : LD Rd, -Y 01793 * Operation : Y <- Y - 1, Rd <- (Y) 01794 * Flags : None 01795 * Num Clocks : 2 01796 */ 01797 uint16_t Y; 01798 01799 int Rd = arg1; 01800 01801 if ((Rd == 28) || (Rd == 29)) 01802 avr_error ("Results of operation are undefined"); 01803 01804 /* Y is R29:R28 */ 01805 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28); 01806 01807 /* Perform pre-decrement */ 01808 Y -= 1; 01809 avr_core_gpwr_set (core, 28, Y & 0xff); 01810 avr_core_gpwr_set (core, 29, Y >> 8); 01811 01812 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Y)); 01813 01814 avr_core_PC_incr (core, 1); 01815 avr_core_inst_CKS_set (core, 2); 01816 01817 return opcode_LD_Y_decr; 01818 } 01819 01820 static int 01821 avr_op_LD_Y_incr (AvrCore *core, uint16_t opcode, unsigned int arg1, 01822 unsigned int arg2) 01823 { 01824 /* 01825 * Load Indirect and Post-Increment using index Y. 01826 * 01827 * Opcode : 1001 000d dddd 1001 01828 * Usage : LD Rd, Y+ 01829 * Operation : Rd <- (Y), Y <- Y + 1 01830 * Flags : None 01831 * Num Clocks : 2 01832 */ 01833 uint16_t Y; 01834 01835 int Rd = arg1; 01836 01837 if ((Rd == 28) || (Rd == 29)) 01838 avr_error ("Results of operation are undefined"); 01839 01840 /* Y is R29:R28 */ 01841 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28); 01842 01843 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Y)); 01844 01845 /* Perform post-increment */ 01846 Y += 1; 01847 avr_core_gpwr_set (core, 28, Y & 0xff); 01848 avr_core_gpwr_set (core, 29, Y >> 8); 01849 01850 avr_core_PC_incr (core, 1); 01851 avr_core_inst_CKS_set (core, 2); 01852 01853 return opcode_LD_Y_incr; 01854 } 01855 01856 static int 01857 avr_op_LD_Z_incr (AvrCore *core, uint16_t opcode, unsigned int arg1, 01858 unsigned int arg2) 01859 { 01860 /* 01861 * Load Indirect and Post-Increment using index Z. 01862 * 01863 * Opcode : 1001 000d dddd 0001 01864 * Usage : LD Rd, Z+ 01865 * Operation : Rd <- (Z), Z <- Z+1 01866 * Flags : None 01867 * Num Clocks : 2 01868 */ 01869 uint16_t Z; 01870 01871 int Rd = arg1; 01872 01873 if ((Rd == 30) || (Rd == 31)) 01874 avr_error ("Results of operation are undefined"); 01875 01876 /* Z is R31:R30 */ 01877 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 01878 01879 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Z)); 01880 01881 /* Perform post-increment */ 01882 Z += 1; 01883 avr_core_gpwr_set (core, 30, Z & 0xff); 01884 avr_core_gpwr_set (core, 31, Z >> 8); 01885 01886 avr_core_PC_incr (core, 1); 01887 avr_core_inst_CKS_set (core, 2); 01888 01889 return opcode_LD_Z_incr; 01890 } 01891 01892 static int 01893 avr_op_LD_Z_decr (AvrCore *core, uint16_t opcode, unsigned int arg1, 01894 unsigned int arg2) 01895 { 01896 /* 01897 * Load Indirect and Pre-Decrement using index Z. 01898 * 01899 * Opcode : 1001 000d dddd 0010 01900 * Usage : LD Rd, -Z 01901 * Operation : Z <- Z - 1, Rd <- (Z) 01902 * Flags : None 01903 * Num Clocks : 2 01904 */ 01905 uint16_t Z; 01906 01907 int Rd = arg1; 01908 01909 if ((Rd == 30) || (Rd == 31)) 01910 avr_error ("Results of operation are undefined"); 01911 01912 /* Z is R31:R30 */ 01913 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 01914 01915 /* Perform pre-decrement */ 01916 Z -= 1; 01917 avr_core_gpwr_set (core, 30, Z & 0xff); 01918 avr_core_gpwr_set (core, 31, Z >> 8); 01919 01920 avr_core_gpwr_set (core, Rd, avr_core_mem_read (core, Z)); 01921 01922 avr_core_PC_incr (core, 1); 01923 avr_core_inst_CKS_set (core, 2); 01924 01925 return opcode_LD_Z_decr; 01926 } 01927 01928 static int 01929 avr_op_LPM_Z (AvrCore *core, uint16_t opcode, unsigned int arg1, 01930 unsigned int arg2) 01931 { 01932 /* 01933 * Load Program Memory. 01934 * 01935 * Opcode : 1001 000d dddd 0100 01936 * Usage : LPM Rd, Z 01937 * Operation : Rd <- (Z) 01938 * Flags : None 01939 * Num Clocks : 3 01940 */ 01941 uint16_t Z, high_byte; 01942 uint16_t data; 01943 01944 int Rd = arg1; 01945 01946 /* Z is R31:R30 */ 01947 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 01948 high_byte = Z & 0x1; 01949 01950 /* FIXME: I don't know if this is the right thing to do. I'm not sure that 01951 I understand what the instruction data sheet is saying about Z. 01952 Dividing by 2 seems to give the address that we want though. */ 01953 01954 data = flash_read (core->flash, Z / 2); 01955 01956 if (high_byte == 1) 01957 avr_core_gpwr_set (core, Rd, data >> 8); 01958 else 01959 avr_core_gpwr_set (core, Rd, data & 0xff); 01960 01961 avr_core_PC_incr (core, 1); 01962 avr_core_inst_CKS_set (core, 3); 01963 01964 return opcode_LPM_Z; 01965 } 01966 01967 static int 01968 avr_op_LPM (AvrCore *core, uint16_t opcode, unsigned int arg1, 01969 unsigned int arg2) 01970 { 01971 /* Load Program Memory. 01972 * 01973 * This the same as avr_op_LPM_Z with Rd = R0. 01974 * 01975 * Opcode : 1001 0101 1100 1000 01976 * Usage : LPM 01977 * Operation : R0 <- (Z) 01978 * Flags : None 01979 * Num Clocks : 3 01980 */ 01981 return avr_op_LPM_Z (core, 0x9004, 0, arg2); 01982 } 01983 01984 static int 01985 avr_op_LPM_Z_incr (AvrCore *core, uint16_t opcode, unsigned int arg1, 01986 unsigned int arg2) 01987 { 01988 /* 01989 * Load Program Memory and Post-Incr. 01990 * 01991 * Opcode : 1001 000d dddd 0101 01992 * Usage : LPM Rd, Z+ 01993 * Operation : Rd <- (Z), Z <- Z + 1 01994 * Flags : None 01995 * Num Clocks : 3 01996 */ 01997 uint16_t Z, high_byte; 01998 uint16_t data; 01999 02000 int Rd = arg1; 02001 02002 if ((Rd == 30) || (Rd == 31)) 02003 avr_error ("Results of operation are undefined"); 02004 02005 /* Z is R31:R30 */ 02006 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 02007 high_byte = Z & 0x1; 02008 02009 /* FIXME: I don't know if this is the right thing to do. I'm not sure that 02010 I understand what the instruction data sheet is saying about Z. 02011 Dividing by 2 seems to give the address that we want though. */ 02012 02013 data = flash_read (core->flash, Z / 2); 02014 02015 if (high_byte == 1) 02016 avr_core_gpwr_set (core, Rd, data >> 8); 02017 else 02018 avr_core_gpwr_set (core, Rd, data & 0xff); 02019 02020 /* Perform post-increment */ 02021 Z += 1; 02022 avr_core_gpwr_set (core, 30, Z & 0xff); 02023 avr_core_gpwr_set (core, 31, Z >> 8); 02024 02025 avr_core_PC_incr (core, 1); 02026 avr_core_inst_CKS_set (core, 3); 02027 02028 return opcode_LPM_Z_incr; 02029 } 02030 02031 static int 02032 avr_op_LSR (AvrCore *core, uint16_t opcode, unsigned int arg1, 02033 unsigned int arg2) 02034 { 02035 /* 02036 * Logical Shift Right. 02037 * 02038 * Opcode : 1001 010d dddd 0110 02039 * Usage : LSR Rd 02040 * Operation : Rd(n) <- Rd(n+1), Rd(7) <- 0, C <- Rd(0) 02041 * Flags : Z,C,N,V,S 02042 * Num Clocks : 1 02043 */ 02044 int Z, C, N, V, S; 02045 02046 int Rd = arg1; 02047 uint8_t rd = avr_core_gpwr_get (core, Rd); 02048 02049 uint8_t res = (rd >> 1) & 0x7f; 02050 02051 uint8_t sreg = avr_core_sreg_get (core); 02052 02053 sreg = set_bit_in_byte (sreg, SREG_C, C = (rd & 0x1)); 02054 sreg = set_bit_in_byte (sreg, SREG_N, N = (0)); 02055 sreg = set_bit_in_byte (sreg, SREG_V, V = (N ^ C)); 02056 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 02057 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 02058 02059 avr_core_sreg_set (core, sreg); 02060 02061 avr_core_gpwr_set (core, Rd, res); 02062 02063 avr_core_PC_incr (core, 1); 02064 avr_core_inst_CKS_set (core, 1); 02065 02066 return opcode_LSR; 02067 } 02068 02069 static int 02070 avr_op_MOV (AvrCore *core, uint16_t opcode, unsigned int arg1, 02071 unsigned int arg2) 02072 { 02073 /* Copy Register. 02074 * 02075 * Opcode : 0010 11rd dddd rrrr 02076 * Usage : MOV Rd, Rr 02077 * Operation : Rd <- Rr 02078 * Flags : None 02079 * Num Clocks : 1 02080 */ 02081 int Rd = arg1; 02082 int Rr = arg2; 02083 02084 avr_core_gpwr_set (core, Rd, avr_core_gpwr_get (core, Rr)); 02085 02086 avr_core_PC_incr (core, 1); 02087 avr_core_inst_CKS_set (core, 1); 02088 02089 return opcode_MOV; 02090 } 02091 02092 static int 02093 avr_op_MOVW (AvrCore *core, uint16_t opcode, unsigned int arg1, 02094 unsigned int arg2) 02095 { 02096 /* 02097 *Copy Register Pair. 02098 * 02099 * Opcode : 0000 0001 dddd rrrr 02100 * Usage : MOVW Rd, Rr 02101 * Operation : Rd+1:Rd <- Rr+1:Rr 02102 * Flags : None 02103 * Num Clocks : 1 02104 */ 02105 int Rd = arg1; 02106 int Rr = arg2; 02107 02108 /* get_rd_4() returns 16 <= r <= 31, but here Rd and Rr */ 02109 /* are even from 0 <= r <= 30. So we translate. */ 02110 Rd = (Rd - 16) * 2; 02111 Rr = (Rr - 16) * 2; 02112 02113 avr_core_gpwr_set (core, Rd, avr_core_gpwr_get (core, Rr)); 02114 avr_core_gpwr_set (core, Rd + 1, avr_core_gpwr_get (core, Rr + 1)); 02115 02116 avr_core_PC_incr (core, 1); 02117 avr_core_inst_CKS_set (core, 1); 02118 02119 return opcode_MOVW; 02120 } 02121 02122 static int 02123 avr_op_MUL (AvrCore *core, uint16_t opcode, unsigned int arg1, 02124 unsigned int arg2) 02125 { 02126 /* 02127 * Mult Unsigned. 02128 * 02129 * Opcode : 1001 11rd dddd rrrr 02130 * Usage : MUL Rd, Rr 02131 * Operation : R1:R0 <- Rd * Rr (UU) 02132 * Flags : Z,C 02133 * Num Clocks : 2 02134 */ 02135 int Rd = arg1; 02136 int Rr = arg2; 02137 02138 uint8_t rd = avr_core_gpwr_get (core, Rd); 02139 uint8_t rr = avr_core_gpwr_get (core, Rr); 02140 02141 uint16_t res = rd * rr; 02142 02143 uint8_t sreg = avr_core_sreg_get (core); 02144 02145 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0)); 02146 sreg = set_bit_in_byte (sreg, SREG_C, ((res >> 15) & 0x1)); 02147 02148 avr_core_sreg_set (core, sreg); 02149 02150 /* result goes in R1:R0 */ 02151 02152 avr_core_gpwr_set (core, 1, res >> 8); 02153 avr_core_gpwr_set (core, 0, res & 0xff); 02154 02155 avr_core_PC_incr (core, 1); 02156 avr_core_inst_CKS_set (core, 2); 02157 02158 return opcode_MUL; 02159 } 02160 02161 static int 02162 avr_op_MULS (AvrCore *core, uint16_t opcode, unsigned int arg1, 02163 unsigned int arg2) 02164 { 02165 /* 02166 * Mult Signed. 02167 * 02168 * Opcode : 0000 0010 dddd rrrr 02169 * Usage : MULS Rd, Rr 02170 * Operation : R1:R0 <- Rd * Rr (SS) 02171 * Flags : Z,C 02172 * Num Clocks : 2 02173 */ 02174 int Rd = arg1; 02175 int Rr = arg2; 02176 02177 int8_t rd = (int8_t) avr_core_gpwr_get (core, Rd); 02178 int8_t rr = (int8_t) avr_core_gpwr_get (core, Rr); 02179 int16_t res = rd * rr; 02180 02181 uint8_t sreg = avr_core_sreg_get (core); 02182 02183 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0)); 02184 sreg = set_bit_in_byte (sreg, SREG_C, ((res >> 15) & 0x1)); 02185 02186 avr_core_sreg_set (core, sreg); 02187 02188 /* result goes in R1:R0 */ 02189 avr_core_gpwr_set (core, 1, res >> 8); 02190 avr_core_gpwr_set (core, 0, res & 0xff); 02191 02192 avr_core_PC_incr (core, 1); 02193 avr_core_inst_CKS_set (core, 2); 02194 02195 return opcode_MULS; 02196 } 02197 02198 static int 02199 avr_op_MULSU (AvrCore *core, uint16_t opcode, unsigned int arg1, 02200 unsigned int arg2) 02201 { 02202 /* 02203 * Mult Signed with Unsigned. 02204 * 02205 * Rd(unsigned),Rr(signed), result (signed) 02206 * 02207 * Opcode : 0000 0011 0ddd 0rrr 02208 * Usage : MULSU Rd, Rr 02209 * Operation : R1:R0 <- Rd * Rr (SU) 02210 * Flags : Z,C 02211 * Num Clocks : 2 02212 */ 02213 int Rd = arg1; 02214 int Rr = arg2; 02215 02216 int8_t rd = (int8_t) avr_core_gpwr_get (core, Rd); 02217 uint8_t rr = avr_core_gpwr_get (core, Rr); 02218 02219 int16_t res = rd * rr; 02220 02221 uint8_t sreg = avr_core_sreg_get (core); 02222 02223 sreg = set_bit_in_byte (sreg, SREG_Z, ((res & 0xffff) == 0)); 02224 sreg = set_bit_in_byte (sreg, SREG_C, ((res >> 15) & 0x1)); 02225 02226 avr_core_sreg_set (core, sreg); 02227 02228 /* result goes in R1:R0 */ 02229 avr_core_gpwr_set (core, 1, res >> 8); 02230 avr_core_gpwr_set (core, 0, res & 0xff); 02231 02232 avr_core_PC_incr (core, 1); 02233 avr_core_inst_CKS_set (core, 2); 02234 02235 return opcode_MULSU; 02236 } 02237 02238 static int 02239 avr_op_NEG (AvrCore *core, uint16_t opcode, unsigned int arg1, 02240 unsigned int arg2) 02241 { 02242 /* 02243 * Two's Complement. 02244 * 02245 * Opcode : 1001 010d dddd 0001 02246 * Usage : NEG Rd 02247 * Operation : Rd <- $00 - Rd 02248 * Flags : Z,C,N,V,S,H 02249 * Num Clocks : 1 02250 */ 02251 int Z, C, N, V, S, H; 02252 02253 int Rd = arg1; 02254 02255 uint8_t rd = avr_core_gpwr_get (core, Rd); 02256 uint8_t res = (0x0 - rd) & 0xff; 02257 02258 uint8_t sreg = avr_core_sreg_get (core); 02259 02260 sreg = set_bit_in_byte (sreg, SREG_H, H = 02261 (((res >> 3) | (rd >> 3)) & 0x1)); 02262 sreg = set_bit_in_byte (sreg, SREG_V, V = (res == 0x80)); 02263 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 02264 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 02265 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (res == 0x0)); 02266 sreg = set_bit_in_byte (sreg, SREG_C, C = (res != 0x0)); 02267 02268 avr_core_sreg_set (core, sreg); 02269 02270 avr_core_gpwr_set (core, Rd, res); 02271 02272 avr_core_PC_incr (core, 1); 02273 avr_core_inst_CKS_set (core, 1); 02274 02275 return opcode_NEG; 02276 } 02277 02278 static int 02279 avr_op_NOP (AvrCore *core, uint16_t opcode, unsigned int arg1, 02280 unsigned int arg2) 02281 { 02282 /* 02283 * No Operation. 02284 * 02285 * Opcode : 0000 0000 0000 0000 02286 * Usage : NOP 02287 * Operation : None 02288 * Flags : None 02289 * Num Clocks : 1 02290 */ 02291 avr_core_PC_incr (core, 1); 02292 avr_core_inst_CKS_set (core, 1); 02293 return opcode_NOP; 02294 } 02295 02296 static int 02297 avr_op_OR (AvrCore *core, uint16_t opcode, unsigned int arg1, 02298 unsigned int arg2) 02299 { 02300 /* 02301 * Logical OR. 02302 * 02303 * Opcode : 0010 10rd dddd rrrr 02304 * Usage : OR Rd, Rr 02305 * Operation : Rd <- Rd or Rr 02306 * Flags : Z,N,V,S 02307 * Num Clocks : 1 02308 */ 02309 int Z, N, V, S; 02310 02311 int Rd = arg1; 02312 int Rr = arg2; 02313 02314 uint8_t res = avr_core_gpwr_get (core, Rd) | avr_core_gpwr_get (core, Rr); 02315 02316 uint8_t sreg = avr_core_sreg_get (core); 02317 02318 sreg = set_bit_in_byte (sreg, SREG_V, V = (0)); 02319 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 02320 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 02321 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (res == 0x0)); 02322 02323 avr_core_sreg_set (core, sreg); 02324 02325 avr_core_gpwr_set (core, Rd, res); 02326 02327 avr_core_PC_incr (core, 1); 02328 avr_core_inst_CKS_set (core, 1); 02329 02330 return opcode_OR; 02331 } 02332 02333 static int 02334 avr_op_ORI (AvrCore *core, uint16_t opcode, unsigned int arg1, 02335 unsigned int arg2) 02336 { 02337 /* 02338 * Logical OR with Immed. 02339 * 02340 * Opcode : 0110 KKKK dddd KKKK 02341 * Usage : ORI Rd, K 02342 * Operation : Rd <- Rd or K 02343 * Flags : Z,N,V,S 02344 * Num Clocks : 1 02345 */ 02346 int Z, N, V, S; 02347 02348 int Rd = arg1; 02349 uint8_t K = arg2; 02350 02351 uint8_t res = avr_core_gpwr_get (core, Rd) | K; 02352 02353 uint8_t sreg = avr_core_sreg_get (core); 02354 02355 sreg = set_bit_in_byte (sreg, SREG_V, V = (0)); 02356 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 02357 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 02358 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (res == 0x0)); 02359 02360 avr_core_sreg_set (core, sreg); 02361 02362 avr_core_gpwr_set (core, Rd, res); 02363 02364 avr_core_PC_incr (core, 1); 02365 avr_core_inst_CKS_set (core, 1); 02366 02367 return opcode_ORI; 02368 } 02369 02370 static int 02371 avr_op_OUT (AvrCore *core, uint16_t opcode, unsigned int arg1, 02372 unsigned int arg2) 02373 { 02374 /* 02375 * Out To I/O Location. 02376 * 02377 * Opcode : 1011 1AAd dddd AAAA 02378 * Usage : OUT A, Rd 02379 * Operation : I/O(A) <- Rd 02380 * Flags : None 02381 * Num Clocks : 1 02382 */ 02383 02384 /* Even though the args in the comment are reversed (out arg2, arg1), the 02385 following is correct: Rd=arg1, A=arg2. */ 02386 int Rd = arg1; 02387 int A = arg2; 02388 02389 avr_core_io_write (core, A, avr_core_gpwr_get (core, Rd)); 02390 02391 avr_core_PC_incr (core, 1); 02392 avr_core_inst_CKS_set (core, 1); 02393 02394 return opcode_OUT; 02395 } 02396 02397 static int 02398 avr_op_POP (AvrCore *core, uint16_t opcode, unsigned int arg1, 02399 unsigned int arg2) 02400 { 02401 /* 02402 * Pop Register from Stack. 02403 * 02404 * Opcode : 1001 000d dddd 1111 02405 * Usage : POP Rd 02406 * Operation : Rd <- STACK 02407 * Flags : None 02408 * Num Clocks : 2 02409 */ 02410 int Rd = arg1; 02411 02412 avr_core_gpwr_set (core, Rd, avr_core_stack_pop (core, 1)); 02413 02414 avr_core_PC_incr (core, 1); 02415 avr_core_inst_CKS_set (core, 2); 02416 02417 return opcode_POP; 02418 } 02419 02420 static int 02421 avr_op_PUSH (AvrCore *core, uint16_t opcode, unsigned int arg1, 02422 unsigned int arg2) 02423 { 02424 /* 02425 * Push Register on Stack. 02426 * 02427 * Opcode : 1001 001d dddd 1111 02428 * Usage : PUSH Rd 02429 * Operation : STACK <- Rd 02430 * Flags : None 02431 * Num Clocks : 2 02432 */ 02433 int Rd = arg1; 02434 02435 avr_core_stack_push (core, 1, avr_core_gpwr_get (core, Rd)); 02436 02437 avr_core_PC_incr (core, 1); 02438 avr_core_inst_CKS_set (core, 2); 02439 02440 return opcode_PUSH; 02441 } 02442 02443 static int 02444 avr_op_RCALL (AvrCore *core, uint16_t opcode, unsigned int arg1, 02445 unsigned int arg2) 02446 { 02447 /* 02448 * Relative Call Subroutine. 02449 * 02450 * Opcode : 1101 kkkk kkkk kkkk 02451 * Usage : RCALL k 02452 * Operation : PC <- PC + k + 1 02453 * Flags : None 02454 * Num Clocks : 3 / 4 02455 */ 02456 int k = arg1; 02457 02458 int pc = avr_core_PC_get (core); 02459 int pc_bytes = avr_core_PC_size (core); 02460 02461 avr_core_stack_push (core, pc_bytes, pc + 1); 02462 02463 avr_core_PC_incr (core, k + 1); 02464 avr_core_inst_CKS_set (core, pc_bytes + 1); 02465 02466 return opcode_RCALL; 02467 } 02468 02469 static int 02470 avr_op_RET (AvrCore *core, uint16_t opcode, unsigned int arg1, 02471 unsigned int arg2) 02472 { 02473 /* 02474 * Subroutine Return. 02475 * 02476 * Opcode : 1001 0101 0000 1000 02477 * Usage : RET 02478 * Operation : PC <- STACK 02479 * Flags : None 02480 * Num Clocks : 4 / 5 02481 */ 02482 int pc_bytes = avr_core_PC_size (core); 02483 int pc = avr_core_stack_pop (core, pc_bytes); 02484 02485 avr_core_PC_set (core, pc); 02486 avr_core_inst_CKS_set (core, pc_bytes + 2); 02487 02488 return opcode_RET; 02489 } 02490 02491 static int 02492 avr_op_RETI (AvrCore *core, uint16_t opcode, unsigned int arg1, 02493 unsigned int arg2) 02494 { 02495 /* 02496 * Interrupt Return. 02497 * 02498 * Opcode : 1001 0101 0001 1000 02499 * Usage : RETI 02500 * Operation : PC <- STACK 02501 * Flags : I 02502 * Num Clocks : 4 / 5 02503 */ 02504 int pc_bytes = avr_core_PC_size (core); 02505 int pc = avr_core_stack_pop (core, pc_bytes); 02506 02507 avr_core_PC_set (core, pc); 02508 avr_core_inst_CKS_set (core, pc_bytes + 2); 02509 02510 avr_core_sreg_set_bit (core, SREG_I, 1); 02511 02512 return opcode_RETI; 02513 } 02514 02515 static int 02516 avr_op_RJMP (AvrCore *core, uint16_t opcode, unsigned int arg1, 02517 unsigned int arg2) 02518 { 02519 /* 02520 * Relative Jump. 02521 * 02522 * Opcode : 1100 kkkk kkkk kkkk 02523 * Usage : RJMP k 02524 * Operation : PC <- PC + k + 1 02525 * Flags : None 02526 * Num Clocks : 2 02527 */ 02528 int k = arg1; 02529 02530 avr_core_PC_incr (core, k + 1); 02531 avr_core_inst_CKS_set (core, 2); 02532 02533 return opcode_RJMP; 02534 } 02535 02536 static int 02537 avr_op_ROR (AvrCore *core, uint16_t opcode, unsigned int arg1, 02538 unsigned int arg2) 02539 { 02540 /* 02541 * Rotate Right Though Carry. 02542 * 02543 * Opcode : 1001 010d dddd 0111 02544 * Usage : ROR Rd 02545 * Operation : Rd(7) <- C, Rd(n) <- Rd(n+1), C <- Rd(0) 02546 * Flags : Z,C,N,V,S 02547 * Num Clocks : 1 02548 */ 02549 int Z, C, N, V, S; 02550 02551 int Rd = arg1; 02552 uint8_t rd = avr_core_gpwr_get (core, Rd); 02553 02554 uint8_t res = 02555 (rd >> 1) | ((avr_core_sreg_get_bit (core, SREG_C) << 7) & 0x80); 02556 02557 uint8_t sreg = avr_core_sreg_get (core); 02558 02559 sreg = set_bit_in_byte (sreg, SREG_C, C = (rd & 0x1)); 02560 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 02561 sreg = set_bit_in_byte (sreg, SREG_V, V = (N ^ C)); 02562 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 02563 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (res == 0)); 02564 02565 avr_core_sreg_set (core, sreg); 02566 02567 avr_core_gpwr_set (core, Rd, res); 02568 02569 avr_core_PC_incr (core, 1); 02570 avr_core_inst_CKS_set (core, 1); 02571 02572 return opcode_ROR; 02573 } 02574 02575 static int 02576 avr_op_SBC (AvrCore *core, uint16_t opcode, unsigned int arg1, 02577 unsigned int arg2) 02578 { 02579 /* 02580 * Subtract with Carry. 02581 * 02582 * Opcode : 0000 10rd dddd rrrr 02583 * Usage : SBC Rd, Rr 02584 * Operation : Rd <- Rd - Rr - C 02585 * Flags : Z,C,N,V,S,H 02586 * Num Clocks : 1 02587 */ 02588 int Z, C, N, V, S, H; 02589 02590 int Rd = arg1; 02591 int Rr = arg2; 02592 02593 uint8_t rd = avr_core_gpwr_get (core, Rd); 02594 uint8_t rr = avr_core_gpwr_get (core, Rr); 02595 02596 uint8_t res = rd - rr - avr_core_sreg_get_bit (core, SREG_C); 02597 02598 uint8_t sreg = avr_core_sreg_get (core); 02599 02600 sreg = set_bit_in_byte (sreg, SREG_H, H = 02601 (get_sub_carry (res, rd, rr, 3))); 02602 sreg = set_bit_in_byte (sreg, SREG_V, V = 02603 (get_sub_overflow (res, rd, rr))); 02604 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 02605 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 02606 sreg = set_bit_in_byte (sreg, SREG_C, C = 02607 (get_sub_carry (res, rd, rr, 7))); 02608 02609 if ((res & 0xff) != 0) 02610 sreg = set_bit_in_byte (sreg, SREG_Z, Z = (0)); 02611 02612 avr_core_sreg_set (core, sreg); 02613 02614 avr_core_gpwr_set (core, Rd, res); 02615 02616 avr_core_PC_incr (core, 1); 02617 avr_core_inst_CKS_set (core, 1); 02618 02619 return opcode_SBC; 02620 } 02621 02622 static int 02623 avr_op_SBCI (AvrCore *core, uint16_t opcode, unsigned int arg1, 02624 unsigned int arg2) 02625 { 02626 /* 02627 * Subtract Immediate with Carry. 02628 * 02629 * Opcode : 0100 KKKK dddd KKKK 02630 * Usage : SBCI Rd, K 02631 * Operation : Rd <- Rd - K - C 02632 * Flags : Z,C,N,V,S,H 02633 * Num Clocks : 1 02634 */ 02635 int Z, C, N, V, S, H; 02636 02637 int Rd = arg1; 02638 uint8_t K = arg2; 02639 02640 uint8_t rd = avr_core_gpwr_get (core, Rd); 02641 02642 uint8_t res = rd - K - avr_core_sreg_get_bit (core, SREG_C); 02643 02644 uint8_t sreg = avr_core_sreg_get (core); 02645 02646 sreg = set_bit_in_byte (sreg, SREG_H, H = 02647 (get_sub_carry (res, rd, K, 3))); 02648 sreg = set_bit_in_byte (sreg, SREG_V, V = 02649 (get_sub_overflow (res, rd, K))); 02650 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 02651 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 02652 sreg = set_bit_in_byte (sreg, SREG_C, C = 02653 (get_sub_carry (res, rd, K, 7))); 02654 02655 if ((res & 0xff) != 0) 02656 sreg = set_bit_in_byte (sreg, SREG_Z, Z = 0); 02657 02658 avr_core_sreg_set (core, sreg); 02659 02660 avr_core_gpwr_set (core, Rd, res); 02661 02662 avr_core_PC_incr (core, 1); 02663 avr_core_inst_CKS_set (core, 1); 02664 02665 return opcode_SBCI; 02666 } 02667 02668 static int 02669 avr_op_SBI (AvrCore *core, uint16_t opcode, unsigned int arg1, 02670 unsigned int arg2) 02671 { 02672 /* 02673 * Set Bit in I/O Register. 02674 * 02675 * Opcode : 1001 1010 AAAA Abbb 02676 * Usage : SBI A, b 02677 * Operation : I/O(A, b) <- 1 02678 * Flags : None 02679 * Num Clocks : 2 02680 */ 02681 int A = arg1; 02682 int b = arg2; 02683 02684 uint8_t val = avr_core_io_read (core, A); 02685 avr_core_io_write (core, A, val | (1 << b)); 02686 02687 avr_core_PC_incr (core, 1); 02688 avr_core_inst_CKS_set (core, 2); 02689 02690 return opcode_SBI; 02691 } 02692 02693 static int 02694 avr_op_SBIC (AvrCore *core, uint16_t opcode, unsigned int arg1, 02695 unsigned int arg2) 02696 { 02697 /* 02698 * Skip if Bit in I/O Reg Cleared. 02699 * 02700 * Opcode : 1001 1001 AAAA Abbb 02701 * Usage : SBIC A, b 02702 * Operation : if (I/O(A,b) = 0) PC <- PC + 2 or 3 02703 * Flags : None 02704 * Num Clocks : 1 / 2 / 3 02705 */ 02706 int skip; 02707 02708 int A = arg1; 02709 int b = arg2; 02710 02711 if (is_next_inst_2_words (core)) 02712 skip = 3; 02713 else 02714 skip = 2; 02715 02716 if ((avr_core_io_read (core, A) & (1 << b)) == 0) 02717 { 02718 avr_core_PC_incr (core, skip); 02719 avr_core_inst_CKS_set (core, skip); 02720 } 02721 else 02722 { 02723 avr_core_PC_incr (core, 1); 02724 avr_core_inst_CKS_set (core, 1); 02725 } 02726 02727 return opcode_SBIC; 02728 } 02729 02730 static int 02731 avr_op_SBIS (AvrCore *core, uint16_t opcode, unsigned int arg1, 02732 unsigned int arg2) 02733 { 02734 /* 02735 * Skip if Bit in I/O Reg Set. 02736 * 02737 * Opcode : 1001 1011 AAAA Abbb 02738 * Usage : SBIS A, b 02739 * Operation : if (I/O(A,b) = 1) PC <- PC + 2 or 3 02740 * Flags : None 02741 * Num Clocks : 1 / 2 / 3 02742 */ 02743 int skip; 02744 02745 int A = arg1; 02746 int b = arg2; 02747 02748 if (is_next_inst_2_words (core)) 02749 skip = 3; 02750 else 02751 skip = 2; 02752 02753 if ((avr_core_io_read (core, A) & (1 << b)) != 0) 02754 { 02755 avr_core_PC_incr (core, skip); 02756 avr_core_inst_CKS_set (core, skip); 02757 } 02758 else 02759 { 02760 avr_core_PC_incr (core, 1); 02761 avr_core_inst_CKS_set (core, 1); 02762 } 02763 02764 return opcode_SBIS; 02765 } 02766 02767 static int 02768 avr_op_SBIW (AvrCore *core, uint16_t opcode, unsigned int arg1, 02769 unsigned int arg2) 02770 { 02771 /* 02772 * Subtract Immed from Word. 02773 * 02774 * Opcode : 1001 0111 KKdd KKKK 02775 * Usage : SBIW Rd, K 02776 * Operation : Rd+1:Rd <- Rd+1:Rd - K 02777 * Flags : Z,C,N,V,S 02778 * Num Clocks : 2 02779 */ 02780 int Z, C, N, V, S; 02781 02782 int Rd = arg1; 02783 uint8_t K = arg2; 02784 02785 uint8_t rdl = avr_core_gpwr_get (core, Rd); 02786 uint8_t rdh = avr_core_gpwr_get (core, Rd + 1); 02787 02788 uint16_t rd = (rdh << 8) + rdl; 02789 02790 uint16_t res = rd - K; 02791 02792 uint8_t sreg = avr_core_sreg_get (core); 02793 02794 sreg = set_bit_in_byte (sreg, SREG_V, V = 02795 ((rdh >> 7 & 0x1) & ~(res >> 15 & 0x1))); 02796 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 15) & 0x1)); 02797 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 02798 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xffff) == 0)); 02799 sreg = set_bit_in_byte (sreg, SREG_C, C = 02800 ((res >> 15 & 0x1) & ~(rdh >> 7 & 0x1))); 02801 02802 avr_core_sreg_set (core, sreg); 02803 02804 avr_core_gpwr_set (core, Rd, res & 0xff); 02805 avr_core_gpwr_set (core, Rd + 1, res >> 8); 02806 02807 avr_core_PC_incr (core, 1); 02808 avr_core_inst_CKS_set (core, 2); 02809 02810 return opcode_SBIW; 02811 } 02812 02813 static int 02814 avr_op_SBRC (AvrCore *core, uint16_t opcode, unsigned int arg1, 02815 unsigned int arg2) 02816 { 02817 /* 02818 * Skip if Bit in Reg Cleared. 02819 * 02820 * Opcode : 1111 110d dddd 0bbb 02821 * Usage : SBRC Rd, b 02822 * Operation : if (Rd(b) = 0) PC <- PC + 2 or 3 02823 * Flags : None 02824 * Num Clocks : 1 / 2 / 3 02825 */ 02826 int skip; 02827 02828 int Rd = arg1; 02829 int b = arg2; 02830 02831 if (is_next_inst_2_words (core)) 02832 skip = 3; 02833 else 02834 skip = 2; 02835 02836 if (((avr_core_gpwr_get (core, Rd) >> b) & 0x1) == 0) 02837 { 02838 avr_core_PC_incr (core, skip); 02839 avr_core_inst_CKS_set (core, skip); 02840 } 02841 else 02842 { 02843 avr_core_PC_incr (core, 1); 02844 avr_core_inst_CKS_set (core, 1); 02845 } 02846 02847 return opcode_SBRC; 02848 } 02849 02850 static int 02851 avr_op_SBRS (AvrCore *core, uint16_t opcode, unsigned int arg1, 02852 unsigned int arg2) 02853 { 02854 /* 02855 * Skip if Bit in Reg Set. 02856 * 02857 * Opcode : 1111 111d dddd 0bbb 02858 * Usage : SBRS Rd, b 02859 * Operation : if (Rd(b) = 1) PC <- PC + 2 or 3 02860 * Flags : None 02861 * Num Clocks : 1 / 2 / 3 02862 */ 02863 int skip; 02864 02865 int Rd = arg1; 02866 int b = arg2; 02867 02868 if (is_next_inst_2_words (core)) 02869 skip = 3; 02870 else 02871 skip = 2; 02872 02873 if (((avr_core_gpwr_get (core, Rd) >> b) & 0x1) != 0) 02874 { 02875 avr_core_PC_incr (core, skip); 02876 avr_core_inst_CKS_set (core, skip); 02877 } 02878 else 02879 { 02880 avr_core_PC_incr (core, 1); 02881 avr_core_inst_CKS_set (core, 1); 02882 } 02883 02884 return opcode_SBRS; 02885 } 02886 02887 static int 02888 avr_op_SLEEP (AvrCore *core, uint16_t opcode, unsigned int arg1, 02889 unsigned int arg2) 02890 { 02891 /* 02892 * Sleep. 02893 * 02894 * This is device specific and should be overridden by sub-class. 02895 * 02896 * Opcode : 1001 0101 1000 1000 02897 * Usage : SLEEP 02898 * Operation : (see specific hardware specification for Sleep) 02899 * Flags : None 02900 * Num Clocks : 1 02901 */ 02902 MCUCR *mcucr = (MCUCR *)avr_core_get_vdev_by_name (core, "MCUCR"); 02903 02904 if (mcucr == NULL) 02905 avr_error ("MCUCR register not installed"); 02906 02907 /* See if sleep mode is enabled */ 02908 if (mcucr_get_bit (mcucr, bit_SE)) 02909 { 02910 if (mcucr_get_bit (mcucr, bit_SM) == 0) 02911 { 02912 /* Idle Mode */ 02913 avr_core_set_sleep_mode (core, SLEEP_MODE_IDLE); 02914 } 02915 else 02916 { 02917 /* Power Down Mode */ 02918 avr_core_set_sleep_mode (core, SLEEP_MODE_PWR_DOWN); 02919 } 02920 } 02921 02922 avr_core_PC_incr (core, 1); 02923 avr_core_inst_CKS_set (core, 1); 02924 02925 return opcode_SLEEP; 02926 } 02927 02928 static int 02929 avr_op_SPM (AvrCore *core, uint16_t opcode, unsigned int arg1, 02930 unsigned int arg2) 02931 { 02932 /* 02933 * Store Program Memory. 02934 * 02935 * Opcode : 1001 0101 1110 1000 02936 * Usage : SPM 02937 * Operation : (Z) <- R1:R0 02938 * Flags : None 02939 * Num Clocks : - 02940 */ 02941 avr_error ("This opcode is not implemented yet: 0x%04x", opcode); 02942 return opcode_SPM; 02943 } 02944 02945 static int 02946 avr_op_STD_Y (AvrCore *core, uint16_t opcode, unsigned int arg1, 02947 unsigned int arg2) 02948 { 02949 /* 02950 * Store Indirect with Displacement. 02951 * 02952 * Opcode : 10q0 qq1d dddd 1qqq 02953 * Usage : STD Y+q, Rd 02954 * Operation : (Y + q) <- Rd 02955 * Flags : None 02956 * Num Clocks : 2 02957 */ 02958 int Y; 02959 02960 int q = arg2; 02961 int Rd = arg1; 02962 02963 /* Y is R29:R28 */ 02964 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28); 02965 02966 avr_core_mem_write (core, Y + q, avr_core_gpwr_get (core, Rd)); 02967 02968 avr_core_PC_incr (core, 1); 02969 avr_core_inst_CKS_set (core, 2); 02970 02971 return opcode_STD_Y; 02972 } 02973 02974 static int 02975 avr_op_STD_Z (AvrCore *core, uint16_t opcode, unsigned int arg1, 02976 unsigned int arg2) 02977 { 02978 /* 02979 * Store Indirect with Displacement. 02980 * 02981 * Opcode : 10q0 qq1d dddd 0qqq 02982 * Usage : STD Z+q, Rd 02983 * Operation : (Z + q) <- Rd 02984 * Flags : None 02985 * Num Clocks : 2 02986 */ 02987 int Z; 02988 02989 int q = arg2; 02990 int Rd = arg1; 02991 02992 /* Z is R31:R30 */ 02993 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 02994 02995 avr_core_mem_write (core, Z + q, avr_core_gpwr_get (core, Rd)); 02996 02997 avr_core_PC_incr (core, 1); 02998 avr_core_inst_CKS_set (core, 2); 02999 03000 return opcode_STD_Z; 03001 } 03002 03003 static int 03004 avr_op_STS (AvrCore *core, uint16_t opcode, unsigned int arg1, 03005 unsigned int arg2) 03006 { 03007 /* 03008 * Store Direct to data space. 03009 * 03010 * Opcode : 1001 001d dddd 0000 kkkk kkkk kkkk kkkk 03011 * Usage : STS k, Rd 03012 * Operation : (k) <- Rd 03013 * Flags : None 03014 * Num Clocks : 2 03015 */ 03016 int Rd = arg1; 03017 03018 /* Get data at k in current data segment and put into Rd */ 03019 int k_pc = avr_core_PC_get (core) + 1; 03020 int k = flash_read (core->flash, k_pc); 03021 03022 avr_core_mem_write (core, k, avr_core_gpwr_get (core, Rd)); 03023 03024 avr_core_PC_incr (core, 2); 03025 avr_core_inst_CKS_set (core, 2); 03026 03027 return opcode_STS; 03028 } 03029 03030 static int 03031 avr_op_ST_X (AvrCore *core, uint16_t opcode, unsigned int arg1, 03032 unsigned int arg2) 03033 { 03034 /* 03035 * Store Indirect using index X. 03036 * 03037 * Opcode : 1001 001d dddd 1100 03038 * Usage : ST X, Rd 03039 * Operation : (X) <- Rd 03040 * Flags : None 03041 * Num Clocks : 2 03042 */ 03043 uint16_t X; 03044 03045 int Rd = arg1; 03046 03047 /* X is R27:R26 */ 03048 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26); 03049 03050 avr_core_mem_write (core, X, avr_core_gpwr_get (core, Rd)); 03051 03052 avr_core_PC_incr (core, 1); 03053 avr_core_inst_CKS_set (core, 2); 03054 03055 return opcode_ST_X; 03056 } 03057 03058 static int 03059 avr_op_ST_X_decr (AvrCore *core, uint16_t opcode, unsigned int arg1, 03060 unsigned int arg2) 03061 { 03062 /* 03063 * Store Indirect and Pre-Decrement using index X. 03064 * 03065 * Opcode : 1001 001d dddd 1110 03066 * Usage : ST -X, Rd 03067 * Operation : X <- X - 1, (X) <- Rd 03068 * Flags : None 03069 * Num Clocks : 2 03070 */ 03071 uint16_t X; 03072 03073 int Rd = arg1; 03074 03075 if ((Rd == 26) || (Rd == 27)) 03076 avr_error ("Results of operation are undefined: 0x%04x", opcode); 03077 03078 /* X is R27:R26 */ 03079 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26); 03080 03081 /* Perform pre-decrement */ 03082 X -= 1; 03083 avr_core_gpwr_set (core, 26, X & 0xff); 03084 avr_core_gpwr_set (core, 27, X >> 8); 03085 03086 avr_core_mem_write (core, X, avr_core_gpwr_get (core, Rd)); 03087 03088 avr_core_PC_incr (core, 1); 03089 avr_core_inst_CKS_set (core, 2); 03090 03091 return opcode_ST_X_decr; 03092 } 03093 03094 static int 03095 avr_op_ST_X_incr (AvrCore *core, uint16_t opcode, unsigned int arg1, 03096 unsigned int arg2) 03097 { 03098 /* 03099 * Store Indirect and Post-Increment using index X. 03100 * 03101 * Opcode : 1001 001d dddd 1101 03102 * Usage : ST X+, Rd 03103 * Operation : (X) <- Rd, X <- X + 1 03104 * Flags : None 03105 * Num Clocks : 2 03106 */ 03107 uint16_t X; 03108 03109 int Rd = arg1; 03110 03111 if ((Rd == 26) || (Rd == 27)) 03112 avr_error ("Results of operation are undefined: 0x%04x", opcode); 03113 03114 /* X is R27:R26 */ 03115 X = (avr_core_gpwr_get (core, 27) << 8) + avr_core_gpwr_get (core, 26); 03116 03117 avr_core_mem_write (core, X, avr_core_gpwr_get (core, Rd)); 03118 03119 /* Perform post-increment */ 03120 X += 1; 03121 avr_core_gpwr_set (core, 26, X & 0xff); 03122 avr_core_gpwr_set (core, 27, X >> 8); 03123 03124 avr_core_PC_incr (core, 1); 03125 avr_core_inst_CKS_set (core, 2); 03126 03127 return opcode_ST_X_incr; 03128 } 03129 03130 static int 03131 avr_op_ST_Y_decr (AvrCore *core, uint16_t opcode, unsigned int arg1, 03132 unsigned int arg2) 03133 { 03134 /* 03135 * Store Indirect and Pre-Decrement using index Y. 03136 * 03137 * Opcode : 1001 001d dddd 1010 03138 * Usage : ST -Y, Rd 03139 * Operation : Y <- Y - 1, (Y) <- Rd 03140 * Flags : None 03141 * Num Clocks : 2 03142 */ 03143 uint16_t Y; 03144 03145 int Rd = arg1; 03146 03147 if ((Rd == 28) || (Rd == 29)) 03148 avr_error ("Results of operation are undefined: 0x%04x", opcode); 03149 03150 /* Y is R29:R28 */ 03151 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28); 03152 03153 /* Perform pre-decrement */ 03154 Y -= 1; 03155 avr_core_gpwr_set (core, 28, Y & 0xff); 03156 avr_core_gpwr_set (core, 29, Y >> 8); 03157 03158 avr_core_mem_write (core, Y, avr_core_gpwr_get (core, Rd)); 03159 03160 avr_core_PC_incr (core, 1); 03161 avr_core_inst_CKS_set (core, 2); 03162 03163 return opcode_ST_Y_decr; 03164 } 03165 03166 static int 03167 avr_op_ST_Y_incr (AvrCore *core, uint16_t opcode, unsigned int arg1, 03168 unsigned int arg2) 03169 { 03170 /* 03171 * Store Indirect and Post-Increment using index Y. 03172 * 03173 * Opcode : 1001 001d dddd 1001 03174 * Usage : ST Y+, Rd 03175 * Operation : (Y) <- Rd, Y <- Y + 1 03176 * Flags : None 03177 * Num Clocks : 2 03178 */ 03179 uint16_t Y; 03180 03181 int Rd = arg1; 03182 03183 if ((Rd == 28) || (Rd == 29)) 03184 avr_error ("Results of operation are undefined: 0x%04x", opcode); 03185 03186 /* Y is R29:R28 */ 03187 Y = (avr_core_gpwr_get (core, 29) << 8) + avr_core_gpwr_get (core, 28); 03188 03189 avr_core_mem_write (core, Y, avr_core_gpwr_get (core, Rd)); 03190 03191 /* Perform post-increment */ 03192 Y += 1; 03193 avr_core_gpwr_set (core, 28, Y & 0xff); 03194 avr_core_gpwr_set (core, 29, Y >> 8); 03195 03196 avr_core_PC_incr (core, 1); 03197 avr_core_inst_CKS_set (core, 2); 03198 03199 return opcode_ST_Y_incr; 03200 } 03201 03202 static int 03203 avr_op_ST_Z_decr (AvrCore *core, uint16_t opcode, unsigned int arg1, 03204 unsigned int arg2) 03205 { 03206 /* 03207 * Store Indirect and Pre-Decrement using index Z. 03208 * 03209 * Opcode : 1001 001d dddd 0010 03210 * Usage : ST -Z, Rd 03211 * Operation : Z <- Z - 1, (Z) <- Rd 03212 * Flags : None 03213 * Num Clocks : 2 03214 */ 03215 uint16_t Z; 03216 03217 int Rd = arg1; 03218 03219 if ((Rd == 30) || (Rd == 31)) 03220 avr_error ("Results of operation are undefined: 0x%04x", opcode); 03221 03222 /* Z is R31:R30 */ 03223 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 03224 03225 /* Perform pre-decrement */ 03226 Z -= 1; 03227 avr_core_gpwr_set (core, 30, Z & 0xff); 03228 avr_core_gpwr_set (core, 31, Z >> 8); 03229 03230 avr_core_mem_write (core, Z, avr_core_gpwr_get (core, Rd)); 03231 03232 avr_core_PC_incr (core, 1); 03233 avr_core_inst_CKS_set (core, 2); 03234 03235 return opcode_ST_Z_decr; 03236 } 03237 03238 static int 03239 avr_op_ST_Z_incr (AvrCore *core, uint16_t opcode, unsigned int arg1, 03240 unsigned int arg2) 03241 { 03242 /* 03243 * Store Indirect and Post-Increment using index Z. 03244 * 03245 * Opcode : 1001 001d dddd 0001 03246 * Usage : ST Z+, Rd 03247 * Operation : (Z) <- Rd, Z <- Z + 1 03248 * Flags : None 03249 * Num Clocks : 2 03250 */ 03251 uint16_t Z; 03252 03253 int Rd = arg1; 03254 03255 if ((Rd == 30) || (Rd == 31)) 03256 avr_error ("Results of operation are undefined: 0x%04x", opcode); 03257 03258 /* Z is R31:R30 */ 03259 Z = (avr_core_gpwr_get (core, 31) << 8) + avr_core_gpwr_get (core, 30); 03260 03261 avr_core_mem_write (core, Z, avr_core_gpwr_get (core, Rd)); 03262 03263 /* Perform post-increment */ 03264 Z += 1; 03265 avr_core_gpwr_set (core, 30, Z & 0xff); 03266 avr_core_gpwr_set (core, 31, Z >> 8); 03267 03268 avr_core_PC_incr (core, 1); 03269 avr_core_inst_CKS_set (core, 2); 03270 03271 return opcode_ST_Z_incr; 03272 } 03273 03274 static int 03275 avr_op_SUB (AvrCore *core, uint16_t opcode, unsigned int arg1, 03276 unsigned int arg2) 03277 { 03278 /* 03279 * Subtract without Carry. 03280 * 03281 * Opcode : 0001 10rd dddd rrrr 03282 * Usage : SUB Rd, Rr 03283 * Operation : Rd <- Rd - Rr 03284 * Flags : Z,C,N,V,S,H 03285 * Num Clocks : 1 03286 */ 03287 int Z, C, N, V, S, H; 03288 03289 int Rd = arg1; 03290 int Rr = arg2; 03291 03292 uint8_t rd = avr_core_gpwr_get (core, Rd); 03293 uint8_t rr = avr_core_gpwr_get (core, Rr); 03294 03295 uint8_t res = rd - rr; 03296 03297 uint8_t sreg = avr_core_sreg_get (core); 03298 03299 sreg = set_bit_in_byte (sreg, SREG_H, H = 03300 (get_sub_carry (res, rd, rr, 3))); 03301 sreg = set_bit_in_byte (sreg, SREG_V, V = 03302 (get_sub_overflow (res, rd, rr))); 03303 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 03304 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 03305 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 03306 sreg = set_bit_in_byte (sreg, SREG_C, C = 03307 (get_sub_carry (res, rd, rr, 7))); 03308 03309 avr_core_sreg_set (core, sreg); 03310 03311 avr_core_gpwr_set (core, Rd, res); 03312 03313 avr_core_PC_incr (core, 1); 03314 avr_core_inst_CKS_set (core, 1); 03315 03316 return opcode_SUB; 03317 } 03318 03319 static int 03320 avr_op_SUBI (AvrCore *core, uint16_t opcode, unsigned int arg1, 03321 unsigned int arg2) 03322 { 03323 /* 03324 * Subtract Immediate. 03325 * 03326 * Opcode : 0101 KKKK dddd KKKK 03327 * Usage : SUBI Rd, K 03328 * Operation : Rd <- Rd - K 03329 * Flags : Z,C,N,V,S,H 03330 * Num Clocks : 1 03331 */ 03332 int Z, C, N, V, S, H; 03333 03334 int Rd = arg1; 03335 uint8_t K = arg2; 03336 03337 uint8_t rd = avr_core_gpwr_get (core, Rd); 03338 03339 uint8_t res = rd - K; 03340 03341 uint8_t sreg = avr_core_sreg_get (core); 03342 03343 sreg = set_bit_in_byte (sreg, SREG_H, H = 03344 (get_sub_carry (res, rd, K, 3))); 03345 sreg = set_bit_in_byte (sreg, SREG_V, V = 03346 (get_sub_overflow (res, rd, K))); 03347 sreg = set_bit_in_byte (sreg, SREG_N, N = ((res >> 7) & 0x1)); 03348 sreg = set_bit_in_byte (sreg, SREG_S, S = (N ^ V)); 03349 sreg = set_bit_in_byte (sreg, SREG_Z, Z = ((res & 0xff) == 0)); 03350 sreg = set_bit_in_byte (sreg, SREG_C, C = 03351 (get_sub_carry (res, rd, K, 7))); 03352 03353 avr_core_sreg_set (core, sreg); 03354 03355 avr_core_gpwr_set (core, Rd, res); 03356 03357 avr_core_PC_incr (core, 1); 03358 avr_core_inst_CKS_set (core, 1); 03359 03360 return opcode_SUBI; 03361 } 03362 03363 static int 03364 avr_op_SWAP (AvrCore *core, uint16_t opcode, unsigned int arg1, 03365 unsigned int arg2) 03366 { 03367 /* 03368 * Swap Nibbles. 03369 * 03370 * Opcode : 1001 010d dddd 0010 03371 * Usage : SWAP Rd 03372 * Operation : Rd(3..0) <--> Rd(7..4) 03373 * Flags : None 03374 * Num Clocks : 1 03375 */ 03376 int Rd = arg1; 03377 uint8_t rd = avr_core_gpwr_get (core, Rd); 03378 03379 avr_core_gpwr_set (core, Rd, ((rd << 4) & 0xf0) | ((rd >> 4) & 0x0f)); 03380 03381 avr_core_PC_incr (core, 1); 03382 avr_core_inst_CKS_set (core, 1); 03383 03384 return opcode_SWAP; 03385 } 03386 03387 static int 03388 avr_op_WDR (AvrCore *core, uint16_t opcode, unsigned int arg1, 03389 unsigned int arg2) 03390 { 03391 /* 03392 * Watchdog Reset. 03393 * 03394 * This is device specific and must be overridden by sub-class. 03395 * 03396 * Opcode : 1001 0101 1010 1000 03397 * Usage : WDR 03398 * Operation : (see specific hardware specification for WDR) 03399 * Flags : None 03400 * Num Clocks : 1 03401 */ 03402 WDTCR *wdtcr = (WDTCR *)avr_core_get_vdev_by_name (core, "WDTCR"); 03403 03404 if (wdtcr == NULL) 03405 avr_error ("Core device doesn't have WDTCR attached"); 03406 03407 wdtcr_update (wdtcr); 03408 03409 avr_core_PC_incr (core, 1); 03410 avr_core_inst_CKS_set (core, 1); 03411 03412 return opcode_WDR; 03413 } 03414 03415 int 03416 avr_op_UNKNOWN (AvrCore *core, uint16_t opcode, unsigned int arg1, 03417 unsigned int arg2) 03418 { 03419 /* 03420 * An unknown opcode was seen. Treat it as a NOP, but return the UNKNOWN 03421 * so that the main loop can issue a warning. 03422 */ 03423 avr_op_NOP (core, opcode, arg1, arg2); 03424 return opcode_UNKNOWN; 03425 } 03426 03427 /******************************************************************************\ 03428 * 03429 * Decode an opcode into the opcode handler function. 03430 * 03431 * Generates a warning and returns NULL if opcode is invalid. 03432 * 03433 * Returns a pointer to the function to handle the opcode. 03434 * 03435 \******************************************************************************/ 03436 03437 static void 03438 lookup_opcode (uint16_t opcode, struct opcode_info *opi) 03439 { 03440 uint16_t decode; 03441 03442 opi->arg1 = -1; 03443 opi->arg2 = -1; 03444 switch (opcode) 03445 { 03446 /* opcodes with no operands */ 03447 case 0x9598: 03448 opi->func = avr_op_BREAK; 03449 return; /* 1001 0101 1001 1000 | BREAK */ 03450 case 0x9519: 03451 opi->func = avr_op_EICALL; 03452 return; /* 1001 0101 0001 1001 | EICALL */ 03453 case 0x9419: 03454 opi->func = avr_op_EIJMP; 03455 return; /* 1001 0100 0001 1001 | EIJMP */ 03456 case 0x95D8: 03457 opi->func = avr_op_ELPM; 03458 return; /* 1001 0101 1101 1000 | ELPM */ 03459 case 0x95F8: 03460 opi->func = avr_op_ESPM; 03461 return; /* 1001 0101 1111 1000 | ESPM */ 03462 case 0x9509: 03463 opi->func = avr_op_ICALL; 03464 return; /* 1001 0101 0000 1001 | ICALL */ 03465 case 0x9409: 03466 opi->func = avr_op_IJMP; 03467 return; /* 1001 0100 0000 1001 | IJMP */ 03468 case 0x95C8: 03469 opi->func = avr_op_LPM; 03470 return; /* 1001 0101 1100 1000 | LPM */ 03471 case 0x0000: 03472 opi->func = avr_op_NOP; 03473 return; /* 0000 0000 0000 0000 | NOP */ 03474 case 0x9508: 03475 opi->func = avr_op_RET; 03476 return; /* 1001 0101 0000 1000 | RET */ 03477 case 0x9518: 03478 opi->func = avr_op_RETI; 03479 return; /* 1001 0101 0001 1000 | RETI */ 03480 case 0x9588: 03481 opi->func = avr_op_SLEEP; 03482 return; /* 1001 0101 1000 1000 | SLEEP */ 03483 case 0x95E8: 03484 opi->func = avr_op_SPM; 03485 return; /* 1001 0101 1110 1000 | SPM */ 03486 case 0x95A8: 03487 opi->func = avr_op_WDR; 03488 return; /* 1001 0101 1010 1000 | WDR */ 03489 03490 default: 03491 { 03492 /* opcodes with two 5-bit register (Rd and Rr) operands */ 03493 decode = opcode & ~(mask_Rd_5 | mask_Rr_5); 03494 opi->arg1 = get_rd_5 (opcode); 03495 opi->arg2 = get_rr_5 (opcode); 03496 switch (decode) 03497 { 03498 case 0x1C00: 03499 opi->func = avr_op_ADC; 03500 return; /* 0001 11rd dddd rrrr | ADC or ROL */ 03501 case 0x0C00: 03502 opi->func = avr_op_ADD; 03503 return; /* 0000 11rd dddd rrrr | ADD or LSL */ 03504 case 0x2000: 03505 opi->func = avr_op_AND; 03506 return; /* 0010 00rd dddd rrrr | AND or TST */ 03507 case 0x1400: 03508 opi->func = avr_op_CP; 03509 return; /* 0001 01rd dddd rrrr | CP */ 03510 case 0x0400: 03511 opi->func = avr_op_CPC; 03512 return; /* 0000 01rd dddd rrrr | CPC */ 03513 case 0x1000: 03514 opi->func = avr_op_CPSE; 03515 return; /* 0001 00rd dddd rrrr | CPSE */ 03516 case 0x2400: 03517 opi->func = avr_op_EOR; 03518 return; /* 0010 01rd dddd rrrr | EOR or CLR */ 03519 case 0x2C00: 03520 opi->func = avr_op_MOV; 03521 return; /* 0010 11rd dddd rrrr | MOV */ 03522 case 0x9C00: 03523 opi->func = avr_op_MUL; 03524 return; /* 1001 11rd dddd rrrr | MUL */ 03525 case 0x2800: 03526 opi->func = avr_op_OR; 03527 return; /* 0010 10rd dddd rrrr | OR */ 03528 case 0x0800: 03529 opi->func = avr_op_SBC; 03530 return; /* 0000 10rd dddd rrrr | SBC */ 03531 case 0x1800: 03532 opi->func = avr_op_SUB; 03533 return; /* 0001 10rd dddd rrrr | SUB */ 03534 } 03535 03536 /* opcode with a single register (Rd) as operand */ 03537 decode = opcode & ~(mask_Rd_5); 03538 opi->arg1 = get_rd_5 (opcode); 03539 opi->arg2 = -1; 03540 switch (decode) 03541 { 03542 case 0x9405: 03543 opi->func = avr_op_ASR; 03544 return; /* 1001 010d dddd 0101 | ASR */ 03545 case 0x9400: 03546 opi->func = avr_op_COM; 03547 return; /* 1001 010d dddd 0000 | COM */ 03548 case 0x940A: 03549 opi->func = avr_op_DEC; 03550 return; /* 1001 010d dddd 1010 | DEC */ 03551 case 0x9006: 03552 opi->func = avr_op_ELPM_Z; 03553 return; /* 1001 000d dddd 0110 | ELPM */ 03554 case 0x9007: 03555 opi->func = avr_op_ELPM_Z_incr; 03556 return; /* 1001 000d dddd 0111 | ELPM */ 03557 case 0x9403: 03558 opi->func = avr_op_INC; 03559 return; /* 1001 010d dddd 0011 | INC */ 03560 case 0x9000: 03561 opi->func = avr_op_LDS; 03562 return; /* 1001 000d dddd 0000 | LDS */ 03563 case 0x900C: 03564 opi->func = avr_op_LD_X; 03565 return; /* 1001 000d dddd 1100 | LD */ 03566 case 0x900E: 03567 opi->func = avr_op_LD_X_decr; 03568 return; /* 1001 000d dddd 1110 | LD */ 03569 case 0x900D: 03570 opi->func = avr_op_LD_X_incr; 03571 return; /* 1001 000d dddd 1101 | LD */ 03572 case 0x900A: 03573 opi->func = avr_op_LD_Y_decr; 03574 return; /* 1001 000d dddd 1010 | LD */ 03575 case 0x9009: 03576 opi->func = avr_op_LD_Y_incr; 03577 return; /* 1001 000d dddd 1001 | LD */ 03578 case 0x9002: 03579 opi->func = avr_op_LD_Z_decr; 03580 return; /* 1001 000d dddd 0010 | LD */ 03581 case 0x9001: 03582 opi->func = avr_op_LD_Z_incr; 03583 return; /* 1001 000d dddd 0001 | LD */ 03584 case 0x9004: 03585 opi->func = avr_op_LPM_Z; 03586 return; /* 1001 000d dddd 0100 | LPM */ 03587 case 0x9005: 03588 opi->func = avr_op_LPM_Z_incr; 03589 return; /* 1001 000d dddd 0101 | LPM */ 03590 case 0x9406: 03591 opi->func = avr_op_LSR; 03592 return; /* 1001 010d dddd 0110 | LSR */ 03593 case 0x9401: 03594 opi->func = avr_op_NEG; 03595 return; /* 1001 010d dddd 0001 | NEG */ 03596 case 0x900F: 03597 opi->func = avr_op_POP; 03598 return; /* 1001 000d dddd 1111 | POP */ 03599 case 0x920F: 03600 opi->func = avr_op_PUSH; 03601 return; /* 1001 001d dddd 1111 | PUSH */ 03602 case 0x9407: 03603 opi->func = avr_op_ROR; 03604 return; /* 1001 010d dddd 0111 | ROR */ 03605 case 0x9200: 03606 opi->func = avr_op_STS; 03607 return; /* 1001 001d dddd 0000 | STS */ 03608 case 0x920C: 03609 opi->func = avr_op_ST_X; 03610 return; /* 1001 001d dddd 1100 | ST */ 03611 case 0x920E: 03612 opi->func = avr_op_ST_X_decr; 03613 return; /* 1001 001d dddd 1110 | ST */ 03614 case 0x920D: 03615 opi->func = avr_op_ST_X_incr; 03616 return; /* 1001 001d dddd 1101 | ST */ 03617 case 0x920A: 03618 opi->func = avr_op_ST_Y_decr; 03619 return; /* 1001 001d dddd 1010 | ST */ 03620 case 0x9209: 03621 opi->func = avr_op_ST_Y_incr; 03622 return; /* 1001 001d dddd 1001 | ST */ 03623 case 0x9202: 03624 opi->func = avr_op_ST_Z_decr; 03625 return; /* 1001 001d dddd 0010 | ST */ 03626 case 0x9201: 03627 opi->func = avr_op_ST_Z_incr; 03628 return; /* 1001 001d dddd 0001 | ST */ 03629 case 0x9402: 03630 opi->func = avr_op_SWAP; 03631 return; /* 1001 010d dddd 0010 | SWAP */ 03632 } 03633 03634 /* opcodes with a register (Rd) and a constant data (K) as 03635 operands */ 03636 decode = opcode & ~(mask_Rd_4 | mask_K_8); 03637 opi->arg1 = get_rd_4 (opcode); 03638 opi->arg2 = get_K_8 (opcode); 03639 switch (decode) 03640 { 03641 case 0x7000: 03642 opi->func = avr_op_ANDI; 03643 return; /* 0111 KKKK dddd KKKK | CBR or ANDI */ 03644 case 0x3000: 03645 opi->func = avr_op_CPI; 03646 return; /* 0011 KKKK dddd KKKK | CPI */ 03647 case 0xE000: 03648 opi->func = avr_op_LDI; 03649 return; /* 1110 KKKK dddd KKKK | LDI or SER */ 03650 case 0x6000: 03651 opi->func = avr_op_ORI; 03652 return; /* 0110 KKKK dddd KKKK | SBR or ORI */ 03653 case 0x4000: 03654 opi->func = avr_op_SBCI; 03655 return; /* 0100 KKKK dddd KKKK | SBCI */ 03656 case 0x5000: 03657 opi->func = avr_op_SUBI; 03658 return; /* 0101 KKKK dddd KKKK | SUBI */ 03659 } 03660 03661 /* opcodes with a register (Rd) and a register bit number (b) 03662 as operands */ 03663 decode = opcode & ~(mask_Rd_5 | mask_reg_bit); 03664 opi->arg1 = get_rd_5 (opcode); 03665 opi->arg2 = get_reg_bit (opcode); 03666 switch (decode) 03667 { 03668 case 0xF800: 03669 opi->func = avr_op_BLD; 03670 return; /* 1111 100d dddd 0bbb | BLD */ 03671 case 0xFA00: 03672 opi->func = avr_op_BST; 03673 return; /* 1111 101d dddd 0bbb | BST */ 03674 case 0xFC00: 03675 opi->func = avr_op_SBRC; 03676 return; /* 1111 110d dddd 0bbb | SBRC */ 03677 case 0xFE00: 03678 opi->func = avr_op_SBRS; 03679 return; /* 1111 111d dddd 0bbb | SBRS */ 03680 } 03681 03682 /* opcodes with a relative 7-bit address (k) and a register 03683 bit number (b) as operands */ 03684 decode = opcode & ~(mask_k_7 | mask_reg_bit); 03685 opi->arg1 = get_reg_bit (opcode); 03686 opi->arg2 = n_bit_unsigned_to_signed (get_k_7 (opcode), 7); 03687 switch (decode) 03688 { 03689 case 0xF400: 03690 opi->func = avr_op_BRBC; 03691 return; /* 1111 01kk kkkk kbbb | BRBC */ 03692 case 0xF000: 03693 opi->func = avr_op_BRBS; 03694 return; /* 1111 00kk kkkk kbbb | BRBS */ 03695 } 03696 03697 /* opcodes with a 6-bit address displacement (q) and a 03698 register (Rd) as operands */ 03699 decode = opcode & ~(mask_Rd_5 | mask_q_displ); 03700 opi->arg1 = get_rd_5 (opcode); 03701 opi->arg2 = get_q (opcode); 03702 switch (decode) 03703 { 03704 case 0x8008: 03705 opi->func = avr_op_LDD_Y; 03706 return; /* 10q0 qq0d dddd 1qqq | LDD */ 03707 case 0x8000: 03708 opi->func = avr_op_LDD_Z; 03709 return; /* 10q0 qq0d dddd 0qqq | LDD */ 03710 case 0x8208: 03711 opi->func = avr_op_STD_Y; 03712 return; /* 10q0 qq1d dddd 1qqq | STD */ 03713 case 0x8200: 03714 opi->func = avr_op_STD_Z; 03715 return; /* 10q0 qq1d dddd 0qqq | STD */ 03716 } 03717 03718 /* opcodes with a absolute 22-bit address (k) operand */ 03719 decode = opcode & ~(mask_k_22); 03720 opi->arg1 = get_k_22 (opcode); 03721 opi->arg2 = -1; 03722 switch (decode) 03723 { 03724 case 0x940E: 03725 opi->func = avr_op_CALL; 03726 return; /* 1001 010k kkkk 111k | CALL */ 03727 case 0x940C: 03728 opi->func = avr_op_JMP; 03729 return; /* 1001 010k kkkk 110k | JMP */ 03730 } 03731 03732 /* opcode with a sreg bit select (s) operand */ 03733 decode = opcode & ~(mask_sreg_bit); 03734 opi->arg1 = get_sreg_bit (opcode); 03735 opi->arg2 = -1; 03736 switch (decode) 03737 { 03738 /* BCLR takes place of CL{C,Z,N,V,S,H,T,I} */ 03739 /* BSET takes place of SE{C,Z,N,V,S,H,T,I} */ 03740 case 0x9488: 03741 opi->func = avr_op_BCLR; 03742 return; /* 1001 0100 1sss 1000 | BCLR */ 03743 case 0x9408: 03744 opi->func = avr_op_BSET; 03745 return; /* 1001 0100 0sss 1000 | BSET */ 03746 } 03747 03748 /* opcodes with a 6-bit constant (K) and a register (Rd) as 03749 operands */ 03750 decode = opcode & ~(mask_K_6 | mask_Rd_2); 03751 opi->arg1 = get_rd_2 (opcode); 03752 opi->arg2 = get_K_6 (opcode); 03753 switch (decode) 03754 { 03755 case 0x9600: 03756 opi->func = avr_op_ADIW; 03757 return; /* 1001 0110 KKdd KKKK | ADIW */ 03758 case 0x9700: 03759 opi->func = avr_op_SBIW; 03760 return; /* 1001 0111 KKdd KKKK | SBIW */ 03761 } 03762 03763 /* opcodes with a 5-bit IO Addr (A) and register bit number 03764 (b) as operands */ 03765 decode = opcode & ~(mask_A_5 | mask_reg_bit); 03766 opi->arg1 = get_A_5 (opcode); 03767 opi->arg2 = get_reg_bit (opcode); 03768 switch (decode) 03769 { 03770 case 0x9800: 03771 opi->func = avr_op_CBI; 03772 return; /* 1001 1000 AAAA Abbb | CBI */ 03773 case 0x9A00: 03774 opi->func = avr_op_SBI; 03775 return; /* 1001 1010 AAAA Abbb | SBI */ 03776 case 0x9900: 03777 opi->func = avr_op_SBIC; 03778 return; /* 1001 1001 AAAA Abbb | SBIC */ 03779 case 0x9B00: 03780 opi->func = avr_op_SBIS; 03781 return; /* 1001 1011 AAAA Abbb | SBIS */ 03782 } 03783 03784 /* opcodes with a 6-bit IO Addr (A) and register (Rd) as 03785 operands */ 03786 decode = opcode & ~(mask_A_6 | mask_Rd_5); 03787 opi->arg1 = get_rd_5 (opcode); 03788 opi->arg2 = get_A_6 (opcode); 03789 switch (decode) 03790 { 03791 case 0xB000: 03792 opi->func = avr_op_IN; 03793 return; /* 1011 0AAd dddd AAAA | IN */ 03794 case 0xB800: 03795 opi->func = avr_op_OUT; 03796 return; /* 1011 1AAd dddd AAAA | OUT */ 03797 } 03798 03799 /* opcodes with a relative 12-bit address (k) operand */ 03800 decode = opcode & ~(mask_k_12); 03801 opi->arg1 = n_bit_unsigned_to_signed (get_k_12 (opcode), 12); 03802 opi->arg2 = -1; 03803 switch (decode) 03804 { 03805 case 0xD000: 03806 opi->func = avr_op_RCALL; 03807 return; /* 1101 kkkk kkkk kkkk | RCALL */ 03808 case 0xC000: 03809 opi->func = avr_op_RJMP; 03810 return; /* 1100 kkkk kkkk kkkk | RJMP */ 03811 } 03812 03813 /* opcodes with two 4-bit register (Rd and Rr) operands */ 03814 decode = opcode & ~(mask_Rd_4 | mask_Rr_4); 03815 opi->arg1 = get_rd_4 (opcode); 03816 opi->arg2 = get_rr_4 (opcode); 03817 switch (decode) 03818 { 03819 case 0x0100: 03820 opi->func = avr_op_MOVW; 03821 return; /* 0000 0001 dddd rrrr | MOVW */ 03822 case 0x0200: 03823 opi->func = avr_op_MULS; 03824 return; /* 0000 0010 dddd rrrr | MULS */ 03825 } 03826 03827 /* opcodes with two 3-bit register (Rd and Rr) operands */ 03828 decode = opcode & ~(mask_Rd_3 | mask_Rr_3); 03829 opi->arg1 = get_rd_3 (opcode); 03830 opi->arg2 = get_rr_3 (opcode); 03831 switch (decode) 03832 { 03833 case 0x0300: 03834 opi->func = avr_op_MULSU; 03835 return; /* 0000 0011 0ddd 0rrr | MULSU */ 03836 case 0x0308: 03837 opi->func = avr_op_FMUL; 03838 return; /* 0000 0011 0ddd 1rrr | FMUL */ 03839 case 0x0380: 03840 opi->func = avr_op_FMULS; 03841 return; /* 0000 0011 1ddd 0rrr | FMULS */ 03842 case 0x0388: 03843 opi->func = avr_op_FMULSU; 03844 return; /* 0000 0011 1ddd 1rrr | FMULSU */ 03845 } 03846 03847 } /* default */ 03848 } /* first switch */ 03849 03850 opi->func = avr_op_UNKNOWN; 03851 opi->arg1 = -1; 03852 opi->arg2 = -1; 03853 03854 } /* decode opcode function */ 03855 03856 /** 03857 * \brief Initialize the decoder lookup table. 03858 * 03859 * This is automatically called by avr_core_construct(). 03860 * 03861 * It is safe to call this function many times, since if will only create the 03862 * table the first time it is called. 03863 */ 03864 03865 void 03866 decode_init_lookup_table (void) 03867 { 03868 if (global_opcode_lookup_table == NULL) 03869 { 03870 int num_ops = 0x10000; 03871 int i; 03872 avr_message ("generating opcode lookup_table\n"); 03873 global_opcode_lookup_table = avr_new0 (struct opcode_info, num_ops); 03874 for (i = 0; i < num_ops; i++) 03875 { 03876 lookup_opcode (i, global_opcode_lookup_table + i); 03877 } 03878 } 03879 } 03880 03881 /** 03882 * \brief Decode an opcode into the opcode handler function. 03883 * 03884 * Generates a warning and returns NULL if opcode is invalid. 03885 * 03886 * Returns a pointer to the function to handle the opcode. 03887 */ 03888 03889 extern inline struct opcode_info *decode_opcode (uint16_t opcode);

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